124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright IBM Corp. 2008
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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#include <asm/tlbflush.h>
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#include "44x_tlb.h"
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/* Note: clearing MSR[DE] just means that the debug interrupt will not be
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* delivered *immediately*. Instead, it simply sets the appropriate DBSR bits.
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* If those DBSR bits are still set when MSR[DE] is re-enabled, the interrupt
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* will be delivered as an "imprecise debug event" (which is indicated by
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* DBSR[IDE].
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*/
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static void kvm44x_disable_debug_interrupts(void)
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{
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mtmsr(mfmsr() & ~MSR_DE);
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}
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void kvmppc_core_load_host_debugstate(struct kvm_vcpu *vcpu)
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{
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kvm44x_disable_debug_interrupts();
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mtspr(SPRN_IAC1, vcpu->arch.host_iac[0]);
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mtspr(SPRN_IAC2, vcpu->arch.host_iac[1]);
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mtspr(SPRN_IAC3, vcpu->arch.host_iac[2]);
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mtspr(SPRN_IAC4, vcpu->arch.host_iac[3]);
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mtspr(SPRN_DBCR1, vcpu->arch.host_dbcr1);
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mtspr(SPRN_DBCR2, vcpu->arch.host_dbcr2);
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mtspr(SPRN_DBCR0, vcpu->arch.host_dbcr0);
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mtmsr(vcpu->arch.host_msr);
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}
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void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu)
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{
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struct kvm_guest_debug *dbg = &vcpu->guest_debug;
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u32 dbcr0 = 0;
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vcpu->arch.host_msr = mfmsr();
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kvm44x_disable_debug_interrupts();
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/* Save host debug register state. */
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vcpu->arch.host_iac[0] = mfspr(SPRN_IAC1);
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vcpu->arch.host_iac[1] = mfspr(SPRN_IAC2);
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vcpu->arch.host_iac[2] = mfspr(SPRN_IAC3);
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vcpu->arch.host_iac[3] = mfspr(SPRN_IAC4);
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vcpu->arch.host_dbcr0 = mfspr(SPRN_DBCR0);
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vcpu->arch.host_dbcr1 = mfspr(SPRN_DBCR1);
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vcpu->arch.host_dbcr2 = mfspr(SPRN_DBCR2);
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/* set registers up for guest */
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if (dbg->bp[0]) {
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mtspr(SPRN_IAC1, dbg->bp[0]);
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dbcr0 |= DBCR0_IAC1 | DBCR0_IDM;
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}
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if (dbg->bp[1]) {
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mtspr(SPRN_IAC2, dbg->bp[1]);
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dbcr0 |= DBCR0_IAC2 | DBCR0_IDM;
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}
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if (dbg->bp[2]) {
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mtspr(SPRN_IAC3, dbg->bp[2]);
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dbcr0 |= DBCR0_IAC3 | DBCR0_IDM;
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}
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if (dbg->bp[3]) {
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mtspr(SPRN_IAC4, dbg->bp[3]);
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dbcr0 |= DBCR0_IAC4 | DBCR0_IDM;
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}
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mtspr(SPRN_DBCR0, dbcr0);
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mtspr(SPRN_DBCR1, 0);
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mtspr(SPRN_DBCR2, 0);
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}
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void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
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int i;
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/* Mark every guest entry in the shadow TLB entry modified, so that they
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* will all be reloaded on the next vcpu run (instead of being
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* demand-faulted). */
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for (i = 0; i <= tlb_44x_hwater; i++)
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kvmppc_tlbe_set_modified(vcpu, i);
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}
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void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
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{
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/* Don't leave guest TLB entries resident when being de-scheduled. */
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/* XXX It would be nice to differentiate between heavyweight exit and
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* sched_out here, since we could avoid the TLB flush for heavyweight
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* exits. */
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_tlbia();
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}
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int kvmppc_core_check_processor_compat(void)
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{
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int r;
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if (strcmp(cur_cpu_spec->platform, "ppc440") == 0)
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r = 0;
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else
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r = -ENOTSUPP;
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return r;
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}
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