2010-05-03 03:10:59 +00:00
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/*
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* Cryptographic API.
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*
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* Support for OMAP SHA1/MD5 HW acceleration.
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*
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* Copyright (c) 2010 Nokia Corporation
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* Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Some ideas are from old omap-sha1-md5.c driver.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/crypto.h>
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#include <linux/cryptohash.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/algapi.h>
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#include <crypto/sha.h>
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#include <crypto/hash.h>
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#include <crypto/internal/hash.h>
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <mach/irqs.h>
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#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
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#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
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#define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE
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#define MD5_DIGEST_SIZE 16
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#define SHA_REG_DIGCNT 0x14
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#define SHA_REG_CTRL 0x18
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#define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
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#define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
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#define SHA_REG_CTRL_ALGO_CONST (1 << 3)
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#define SHA_REG_CTRL_ALGO (1 << 2)
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#define SHA_REG_CTRL_INPUT_READY (1 << 1)
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#define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
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#define SHA_REG_REV 0x5C
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#define SHA_REG_REV_MAJOR 0xF0
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#define SHA_REG_REV_MINOR 0x0F
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#define SHA_REG_MASK 0x60
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#define SHA_REG_MASK_DMA_EN (1 << 3)
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#define SHA_REG_MASK_IT_EN (1 << 2)
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#define SHA_REG_MASK_SOFTRESET (1 << 1)
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#define SHA_REG_AUTOIDLE (1 << 0)
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#define SHA_REG_SYSSTATUS 0x64
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#define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
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#define DEFAULT_TIMEOUT_INTERVAL HZ
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2011-06-02 18:10:05 +00:00
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/* mostly device flags */
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#define FLAGS_BUSY 0
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#define FLAGS_FINAL 1
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#define FLAGS_DMA_ACTIVE 2
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#define FLAGS_OUTPUT_READY 3
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#define FLAGS_INIT 4
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#define FLAGS_CPU 5
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/* context flags */
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#define FLAGS_FINUP 16
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#define FLAGS_SG 17
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#define FLAGS_SHA1 18
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#define FLAGS_HMAC 19
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#define FLAGS_ERROR 20
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2010-05-03 03:10:59 +00:00
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#define OP_UPDATE 1
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#define OP_FINAL 2
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2010-11-19 14:04:26 +00:00
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#define OMAP_ALIGN_MASK (sizeof(u32)-1)
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#define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
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#define BUFLEN PAGE_SIZE
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2010-05-03 03:10:59 +00:00
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struct omap_sham_dev;
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struct omap_sham_reqctx {
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struct omap_sham_dev *dd;
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unsigned long flags;
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unsigned long op;
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2010-11-19 14:04:26 +00:00
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u8 digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
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2010-05-03 03:10:59 +00:00
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size_t digcnt;
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size_t bufcnt;
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size_t buflen;
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dma_addr_t dma_addr;
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/* walk state */
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struct scatterlist *sg;
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unsigned int offset; /* offset in current sg */
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unsigned int total; /* total request */
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2010-11-19 14:04:26 +00:00
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u8 buffer[0] OMAP_ALIGNED;
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2010-05-03 03:10:59 +00:00
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};
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struct omap_sham_hmac_ctx {
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struct crypto_shash *shash;
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u8 ipad[SHA1_MD5_BLOCK_SIZE];
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u8 opad[SHA1_MD5_BLOCK_SIZE];
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};
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struct omap_sham_ctx {
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struct omap_sham_dev *dd;
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unsigned long flags;
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/* fallback stuff */
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struct crypto_shash *fallback;
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struct omap_sham_hmac_ctx base[0];
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};
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#define OMAP_SHAM_QUEUE_LENGTH 1
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struct omap_sham_dev {
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struct list_head list;
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unsigned long phys_base;
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struct device *dev;
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void __iomem *io_base;
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int irq;
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struct clk *iclk;
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spinlock_t lock;
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2010-11-19 14:04:24 +00:00
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int err;
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2010-05-03 03:10:59 +00:00
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int dma;
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int dma_lch;
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struct tasklet_struct done_task;
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unsigned long flags;
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struct crypto_queue queue;
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struct ahash_request *req;
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};
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struct omap_sham_drv {
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struct list_head dev_list;
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spinlock_t lock;
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unsigned long flags;
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};
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static struct omap_sham_drv sham = {
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.dev_list = LIST_HEAD_INIT(sham.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(sham.lock),
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};
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static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
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{
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return __raw_readl(dd->io_base + offset);
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}
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static inline void omap_sham_write(struct omap_sham_dev *dd,
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u32 offset, u32 value)
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{
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__raw_writel(value, dd->io_base + offset);
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}
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static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
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u32 value, u32 mask)
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{
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u32 val;
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val = omap_sham_read(dd, address);
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val &= ~mask;
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val |= value;
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omap_sham_write(dd, address, val);
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}
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static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
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{
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unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
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while (!(omap_sham_read(dd, offset) & bit)) {
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if (time_is_before_jiffies(timeout))
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void omap_sham_copy_hash(struct ahash_request *req, int out)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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2010-11-19 14:04:22 +00:00
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u32 *hash = (u32 *)ctx->digest;
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2010-05-03 03:10:59 +00:00
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int i;
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2010-11-19 14:04:27 +00:00
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/* MD5 is almost unused. So copy sha1 size to reduce code */
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
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if (out)
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hash[i] = omap_sham_read(ctx->dd,
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SHA_REG_DIGEST(i));
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else
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omap_sham_write(ctx->dd,
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SHA_REG_DIGEST(i), hash[i]);
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}
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}
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static void omap_sham_copy_ready_hash(struct ahash_request *req)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
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u32 *in = (u32 *)ctx->digest;
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u32 *hash = (u32 *)req->result;
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int i;
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if (!hash)
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return;
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2011-06-02 18:10:05 +00:00
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if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
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2010-05-03 03:10:59 +00:00
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/* SHA1 results are in big endian */
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
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2010-11-19 14:04:27 +00:00
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hash[i] = be32_to_cpu(in[i]);
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2010-05-03 03:10:59 +00:00
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} else {
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/* MD5 results are in little endian */
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for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
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2010-11-19 14:04:27 +00:00
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hash[i] = le32_to_cpu(in[i]);
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2010-05-03 03:10:59 +00:00
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}
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}
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2010-11-19 14:04:26 +00:00
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static int omap_sham_hw_init(struct omap_sham_dev *dd)
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2010-05-03 03:10:59 +00:00
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{
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2010-11-19 14:04:26 +00:00
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clk_enable(dd->iclk);
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2010-05-03 03:10:59 +00:00
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2011-06-02 18:10:06 +00:00
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if (!test_bit(FLAGS_INIT, &dd->flags)) {
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2010-11-19 14:04:26 +00:00
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omap_sham_write_mask(dd, SHA_REG_MASK,
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SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
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2010-05-03 03:10:59 +00:00
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2010-11-19 14:04:26 +00:00
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if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
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SHA_REG_SYSSTATUS_RESETDONE))
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return -ETIMEDOUT;
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2010-05-03 03:10:59 +00:00
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2011-06-02 18:10:06 +00:00
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set_bit(FLAGS_INIT, &dd->flags);
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2010-11-19 14:04:26 +00:00
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dd->err = 0;
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}
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2010-05-03 03:10:59 +00:00
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2010-11-19 14:04:26 +00:00
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return 0;
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}
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static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
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int final, int dma)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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u32 val = length << 5, mask;
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if (likely(ctx->digcnt))
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2010-05-03 03:10:59 +00:00
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omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
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omap_sham_write_mask(dd, SHA_REG_MASK,
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SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
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SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
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/*
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* Setting ALGO_CONST only for the first iteration
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* and CLOSE_HASH only for the last one.
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*/
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2011-06-02 18:10:05 +00:00
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if (ctx->flags & BIT(FLAGS_SHA1))
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2010-05-03 03:10:59 +00:00
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val |= SHA_REG_CTRL_ALGO;
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if (!ctx->digcnt)
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val |= SHA_REG_CTRL_ALGO_CONST;
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if (final)
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val |= SHA_REG_CTRL_CLOSE_HASH;
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mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
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SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
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omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
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}
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static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
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size_t length, int final)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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2010-11-19 14:04:26 +00:00
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int count, len32;
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2010-05-03 03:10:59 +00:00
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const u32 *buffer = (const u32 *)buf;
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dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
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ctx->digcnt, length, final);
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2010-11-19 14:04:26 +00:00
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omap_sham_write_ctrl(dd, length, final, 0);
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2010-05-03 03:10:59 +00:00
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2010-11-19 14:04:24 +00:00
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/* should be non-zero before next lines to disable clocks later */
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ctx->digcnt += length;
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2010-05-03 03:10:59 +00:00
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if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
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return -ETIMEDOUT;
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if (final)
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2011-06-02 18:10:07 +00:00
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set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
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2010-05-03 03:10:59 +00:00
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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for (count = 0; count < len32; count++)
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omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
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return -EINPROGRESS;
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}
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static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
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size_t length, int final)
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{
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struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
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2010-11-19 14:04:26 +00:00
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int len32;
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2010-05-03 03:10:59 +00:00
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dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
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ctx->digcnt, length, final);
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
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2010-09-03 11:20:19 +00:00
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1, OMAP_DMA_SYNC_PACKET, dd->dma,
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OMAP_DMA_DST_SYNC_PREFETCH);
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2010-05-03 03:10:59 +00:00
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omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
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dma_addr, 0, 0);
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2010-11-19 14:04:26 +00:00
|
|
|
omap_sham_write_ctrl(dd, length, final, 1);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
ctx->digcnt += length;
|
|
|
|
|
|
|
|
if (final)
|
2011-06-02 18:10:07 +00:00
|
|
|
set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-06-02 18:10:06 +00:00
|
|
|
set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
omap_start_dma(dd->dma_lch);
|
|
|
|
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
|
|
|
|
const u8 *data, size_t length)
|
|
|
|
{
|
|
|
|
size_t count = min(length, ctx->buflen - ctx->bufcnt);
|
|
|
|
|
|
|
|
count = min(count, ctx->total);
|
|
|
|
if (count <= 0)
|
|
|
|
return 0;
|
|
|
|
memcpy(ctx->buffer + ctx->bufcnt, data, count);
|
|
|
|
ctx->bufcnt += count;
|
|
|
|
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
|
|
|
|
{
|
|
|
|
size_t count;
|
|
|
|
|
|
|
|
while (ctx->sg) {
|
|
|
|
count = omap_sham_append_buffer(ctx,
|
|
|
|
sg_virt(ctx->sg) + ctx->offset,
|
|
|
|
ctx->sg->length - ctx->offset);
|
|
|
|
if (!count)
|
|
|
|
break;
|
|
|
|
ctx->offset += count;
|
|
|
|
ctx->total -= count;
|
|
|
|
if (ctx->offset == ctx->sg->length) {
|
|
|
|
ctx->sg = sg_next(ctx->sg);
|
|
|
|
if (ctx->sg)
|
|
|
|
ctx->offset = 0;
|
|
|
|
else
|
|
|
|
ctx->total = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-19 14:04:26 +00:00
|
|
|
static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
|
|
|
|
struct omap_sham_reqctx *ctx,
|
|
|
|
size_t length, int final)
|
|
|
|
{
|
|
|
|
ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
|
|
|
|
dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags &= ~BIT(FLAGS_SG);
|
2010-11-19 14:04:29 +00:00
|
|
|
|
2010-11-19 14:04:26 +00:00
|
|
|
/* next call does not fail... so no unmap in the case of error */
|
|
|
|
return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
|
|
|
|
}
|
|
|
|
|
2010-05-03 03:10:59 +00:00
|
|
|
static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
|
|
|
unsigned int final;
|
|
|
|
size_t count;
|
|
|
|
|
|
|
|
omap_sham_append_sg(ctx);
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
|
|
|
|
ctx->bufcnt, ctx->digcnt, final);
|
|
|
|
|
|
|
|
if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
|
|
|
|
count = ctx->bufcnt;
|
|
|
|
ctx->bufcnt = 0;
|
2010-11-19 14:04:26 +00:00
|
|
|
return omap_sham_xmit_dma_map(dd, ctx, count, final);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-11-19 14:04:29 +00:00
|
|
|
/* Start address alignment */
|
|
|
|
#define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
|
|
|
|
/* SHA1 block size alignment */
|
|
|
|
#define SG_SA(sg) (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
|
|
|
|
|
|
|
|
static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
|
2010-05-03 03:10:59 +00:00
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
2010-11-19 14:04:29 +00:00
|
|
|
unsigned int length, final, tail;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
|
|
|
|
if (!ctx->total)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (ctx->bufcnt || ctx->offset)
|
|
|
|
return omap_sham_update_dma_slow(dd);
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
|
|
|
|
ctx->digcnt, ctx->bufcnt, ctx->total);
|
|
|
|
|
|
|
|
sg = ctx->sg;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2010-11-19 14:04:29 +00:00
|
|
|
if (!SG_AA(sg))
|
|
|
|
return omap_sham_update_dma_slow(dd);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2010-11-19 14:04:29 +00:00
|
|
|
if (!sg_is_last(sg) && !SG_SA(sg))
|
|
|
|
/* size is not SHA1_BLOCK_SIZE aligned */
|
|
|
|
return omap_sham_update_dma_slow(dd);
|
|
|
|
|
|
|
|
length = min(ctx->total, sg->length);
|
|
|
|
|
|
|
|
if (sg_is_last(sg)) {
|
2011-06-02 18:10:05 +00:00
|
|
|
if (!(ctx->flags & BIT(FLAGS_FINUP))) {
|
2010-11-19 14:04:29 +00:00
|
|
|
/* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
|
|
|
|
tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
|
|
|
|
/* without finup() we need one block to close hash */
|
|
|
|
if (!tail)
|
|
|
|
tail = SHA1_MD5_BLOCK_SIZE;
|
|
|
|
length -= tail;
|
|
|
|
}
|
|
|
|
}
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
|
|
|
|
dev_err(dd->dev, "dma_map_sg error\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_SG);
|
2010-11-19 14:04:29 +00:00
|
|
|
|
2010-05-03 03:10:59 +00:00
|
|
|
ctx->total -= length;
|
2010-11-19 14:04:29 +00:00
|
|
|
ctx->offset = length; /* offset where to start slow */
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2010-11-19 14:04:26 +00:00
|
|
|
/* next call does not fail... so no unmap in the case of error */
|
2010-11-19 14:04:29 +00:00
|
|
|
return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_update_cpu(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
|
|
|
int bufcnt;
|
|
|
|
|
|
|
|
omap_sham_append_sg(ctx);
|
|
|
|
bufcnt = ctx->bufcnt;
|
|
|
|
ctx->bufcnt = 0;
|
|
|
|
|
|
|
|
return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
|
|
|
|
|
|
|
|
omap_stop_dma(dd->dma_lch);
|
2011-06-02 18:10:05 +00:00
|
|
|
if (ctx->flags & BIT(FLAGS_SG)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
|
2010-11-19 14:04:29 +00:00
|
|
|
if (ctx->sg->length == ctx->offset) {
|
|
|
|
ctx->sg = sg_next(ctx->sg);
|
|
|
|
if (ctx->sg)
|
|
|
|
ctx->offset = 0;
|
|
|
|
}
|
|
|
|
} else {
|
2010-11-19 14:04:26 +00:00
|
|
|
dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
|
|
|
|
DMA_TO_DEVICE);
|
2010-11-19 14:04:29 +00:00
|
|
|
}
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_init(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
struct omap_sham_dev *dd = NULL, *tmp;
|
|
|
|
|
|
|
|
spin_lock_bh(&sham.lock);
|
|
|
|
if (!tctx->dd) {
|
|
|
|
list_for_each_entry(tmp, &sham.dev_list, list) {
|
|
|
|
dd = tmp;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
tctx->dd = dd;
|
|
|
|
} else {
|
|
|
|
dd = tctx->dd;
|
|
|
|
}
|
|
|
|
spin_unlock_bh(&sham.lock);
|
|
|
|
|
|
|
|
ctx->dd = dd;
|
|
|
|
|
|
|
|
ctx->flags = 0;
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "init: digest size: %d\n",
|
|
|
|
crypto_ahash_digestsize(tfm));
|
|
|
|
|
|
|
|
if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_SHA1);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
ctx->bufcnt = 0;
|
|
|
|
ctx->digcnt = 0;
|
2010-11-19 14:04:26 +00:00
|
|
|
ctx->buflen = BUFLEN;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
if (tctx->flags & BIT(FLAGS_HMAC)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
|
|
|
|
|
|
memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
|
|
|
|
ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_HMAC);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_update_req(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
struct ahash_request *req = dd->req;
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
if (ctx->flags & BIT(FLAGS_CPU))
|
2010-05-03 03:10:59 +00:00
|
|
|
err = omap_sham_update_cpu(dd);
|
|
|
|
else
|
2010-11-19 14:04:29 +00:00
|
|
|
err = omap_sham_update_dma_start(dd);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
/* wait for dma completion before can take more data */
|
|
|
|
dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_final_req(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
struct ahash_request *req = dd->req;
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
int err = 0, use_dma = 1;
|
|
|
|
|
|
|
|
if (ctx->bufcnt <= 64)
|
|
|
|
/* faster to handle last block with cpu */
|
|
|
|
use_dma = 0;
|
|
|
|
|
|
|
|
if (use_dma)
|
2010-11-19 14:04:26 +00:00
|
|
|
err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
|
2010-05-03 03:10:59 +00:00
|
|
|
else
|
|
|
|
err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
|
|
|
|
|
|
|
|
ctx->bufcnt = 0;
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "final_req: err: %d\n", err);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2011-04-20 10:34:58 +00:00
|
|
|
static int omap_sham_finish_hmac(struct ahash_request *req)
|
2010-05-03 03:10:59 +00:00
|
|
|
{
|
|
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
|
|
int bs = crypto_shash_blocksize(bctx->shash);
|
|
|
|
int ds = crypto_shash_digestsize(bctx->shash);
|
|
|
|
struct {
|
|
|
|
struct shash_desc shash;
|
|
|
|
char ctx[crypto_shash_descsize(bctx->shash)];
|
|
|
|
} desc;
|
|
|
|
|
|
|
|
desc.shash.tfm = bctx->shash;
|
|
|
|
desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
|
|
|
|
|
|
|
|
return crypto_shash_init(&desc.shash) ?:
|
|
|
|
crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
|
2011-04-20 10:34:58 +00:00
|
|
|
crypto_shash_finup(&desc.shash, req->result, ds, req->result);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_finish(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
struct omap_sham_dev *dd = ctx->dd;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (ctx->digcnt) {
|
|
|
|
omap_sham_copy_ready_hash(req);
|
2011-06-02 18:10:05 +00:00
|
|
|
if (ctx->flags & BIT(FLAGS_HMAC))
|
2011-04-20 10:34:58 +00:00
|
|
|
err = omap_sham_finish_hmac(req);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
|
|
|
|
|
|
|
|
return err;
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void omap_sham_finish_req(struct ahash_request *req, int err)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
2010-11-19 14:04:26 +00:00
|
|
|
struct omap_sham_dev *dd = ctx->dd;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
if (!err) {
|
2011-06-02 18:10:03 +00:00
|
|
|
omap_sham_copy_hash(req, 1);
|
2011-06-02 18:10:07 +00:00
|
|
|
if (test_bit(FLAGS_FINAL, &dd->flags))
|
2011-04-20 10:34:58 +00:00
|
|
|
err = omap_sham_finish(req);
|
2010-11-19 14:04:24 +00:00
|
|
|
} else {
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_ERROR);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
2010-11-19 14:04:26 +00:00
|
|
|
clk_disable(dd->iclk);
|
2011-06-02 18:10:05 +00:00
|
|
|
dd->flags &= ~BIT(FLAGS_BUSY);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
if (req->base.complete)
|
|
|
|
req->base.complete(&req->base, err);
|
2011-06-02 18:10:09 +00:00
|
|
|
|
|
|
|
/* handle new request */
|
|
|
|
tasklet_schedule(&dd->done_task);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
2010-11-19 14:04:25 +00:00
|
|
|
static int omap_sham_handle_queue(struct omap_sham_dev *dd,
|
|
|
|
struct ahash_request *req)
|
2010-05-03 03:10:59 +00:00
|
|
|
{
|
2010-12-29 10:52:04 +00:00
|
|
|
struct crypto_async_request *async_req, *backlog;
|
2010-05-03 03:10:59 +00:00
|
|
|
struct omap_sham_reqctx *ctx;
|
|
|
|
unsigned long flags;
|
2010-11-19 14:04:25 +00:00
|
|
|
int err = 0, ret = 0;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dd->lock, flags);
|
2010-11-19 14:04:25 +00:00
|
|
|
if (req)
|
|
|
|
ret = ahash_enqueue_request(&dd->queue, req);
|
2011-06-02 18:10:06 +00:00
|
|
|
if (test_bit(FLAGS_BUSY, &dd->flags)) {
|
2010-11-19 14:04:25 +00:00
|
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
2010-12-29 10:52:04 +00:00
|
|
|
backlog = crypto_get_backlog(&dd->queue);
|
2010-05-03 03:10:59 +00:00
|
|
|
async_req = crypto_dequeue_request(&dd->queue);
|
2010-12-29 10:52:04 +00:00
|
|
|
if (async_req)
|
2011-06-02 18:10:06 +00:00
|
|
|
set_bit(FLAGS_BUSY, &dd->flags);
|
2010-05-03 03:10:59 +00:00
|
|
|
spin_unlock_irqrestore(&dd->lock, flags);
|
|
|
|
|
|
|
|
if (!async_req)
|
2010-11-19 14:04:25 +00:00
|
|
|
return ret;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
if (backlog)
|
|
|
|
backlog->complete(backlog, -EINPROGRESS);
|
|
|
|
|
|
|
|
req = ahash_request_cast(async_req);
|
|
|
|
dd->req = req;
|
|
|
|
ctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
|
|
|
|
ctx->op, req->nbytes);
|
|
|
|
|
2010-11-19 14:04:26 +00:00
|
|
|
err = omap_sham_hw_init(dd);
|
|
|
|
if (err)
|
|
|
|
goto err1;
|
|
|
|
|
|
|
|
omap_set_dma_dest_params(dd->dma_lch, 0,
|
|
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
|
|
dd->phys_base + SHA_REG_DIN(0), 0, 16);
|
|
|
|
|
|
|
|
omap_set_dma_dest_burst_mode(dd->dma_lch,
|
|
|
|
OMAP_DMA_DATA_BURST_16);
|
|
|
|
|
|
|
|
omap_set_dma_src_burst_mode(dd->dma_lch,
|
|
|
|
OMAP_DMA_DATA_BURST_4);
|
|
|
|
|
|
|
|
if (ctx->digcnt)
|
2010-05-03 03:10:59 +00:00
|
|
|
/* request has changed - restore hash */
|
|
|
|
omap_sham_copy_hash(req, 0);
|
|
|
|
|
|
|
|
if (ctx->op == OP_UPDATE) {
|
|
|
|
err = omap_sham_update_req(dd);
|
2011-06-02 18:10:05 +00:00
|
|
|
if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
|
2010-05-03 03:10:59 +00:00
|
|
|
/* no final() after finup() */
|
|
|
|
err = omap_sham_final_req(dd);
|
|
|
|
} else if (ctx->op == OP_FINAL) {
|
|
|
|
err = omap_sham_final_req(dd);
|
|
|
|
}
|
2010-11-19 14:04:26 +00:00
|
|
|
err1:
|
2011-06-02 18:10:09 +00:00
|
|
|
if (err != -EINPROGRESS)
|
2010-05-03 03:10:59 +00:00
|
|
|
/* done_task will not finish it, so do it here */
|
|
|
|
omap_sham_finish_req(req, err);
|
|
|
|
|
|
|
|
dev_dbg(dd->dev, "exit, err: %d\n", err);
|
|
|
|
|
2010-11-19 14:04:25 +00:00
|
|
|
return ret;
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
|
|
struct omap_sham_dev *dd = tctx->dd;
|
|
|
|
|
|
|
|
ctx->op = op;
|
|
|
|
|
2010-11-19 14:04:25 +00:00
|
|
|
return omap_sham_handle_queue(dd, req);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_update(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (!req->nbytes)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ctx->total = req->nbytes;
|
|
|
|
ctx->sg = req->src;
|
|
|
|
ctx->offset = 0;
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
if (ctx->flags & BIT(FLAGS_FINUP)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
|
|
|
|
/*
|
|
|
|
* OMAP HW accel works only with buffers >= 9
|
|
|
|
* will switch to bypass in final()
|
|
|
|
* final has the same request and data
|
|
|
|
*/
|
|
|
|
omap_sham_append_sg(ctx);
|
|
|
|
return 0;
|
2010-11-19 14:04:29 +00:00
|
|
|
} else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
|
|
|
|
/*
|
|
|
|
* faster to use CPU for short transfers
|
|
|
|
*/
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_CPU);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
2010-11-19 14:04:29 +00:00
|
|
|
} else if (ctx->bufcnt + ctx->total < ctx->buflen) {
|
2010-05-03 03:10:59 +00:00
|
|
|
omap_sham_append_sg(ctx);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return omap_sham_enqueue(req, OP_UPDATE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
|
|
|
|
const u8 *data, unsigned int len, u8 *out)
|
|
|
|
{
|
|
|
|
struct {
|
|
|
|
struct shash_desc shash;
|
|
|
|
char ctx[crypto_shash_descsize(shash)];
|
|
|
|
} desc;
|
|
|
|
|
|
|
|
desc.shash.tfm = shash;
|
|
|
|
desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
|
|
|
|
|
|
|
|
return crypto_shash_digest(&desc.shash, data, len, out);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_final_shash(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
return omap_sham_shash_digest(tctx->fallback, req->base.flags,
|
|
|
|
ctx->buffer, ctx->bufcnt, req->result);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_final(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_FINUP);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
if (ctx->flags & BIT(FLAGS_ERROR))
|
2011-04-20 10:34:58 +00:00
|
|
|
return 0; /* uncompleted hash is not needed */
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-04-20 10:34:58 +00:00
|
|
|
/* OMAP HW accel works only with buffers >= 9 */
|
|
|
|
/* HMAC is always >= 9 because ipad == block size */
|
|
|
|
if ((ctx->digcnt + ctx->bufcnt) < 9)
|
|
|
|
return omap_sham_final_shash(req);
|
|
|
|
else if (ctx->bufcnt)
|
|
|
|
return omap_sham_enqueue(req, OP_FINAL);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-04-20 10:34:58 +00:00
|
|
|
/* copy ready hash (+ finalize hmac) */
|
|
|
|
return omap_sham_finish(req);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_finup(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
|
|
|
|
int err1, err2;
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
ctx->flags |= BIT(FLAGS_FINUP);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
err1 = omap_sham_update(req);
|
2011-04-20 10:34:55 +00:00
|
|
|
if (err1 == -EINPROGRESS || err1 == -EBUSY)
|
2010-05-03 03:10:59 +00:00
|
|
|
return err1;
|
|
|
|
/*
|
|
|
|
* final() has to be always called to cleanup resources
|
|
|
|
* even if udpate() failed, except EINPROGRESS
|
|
|
|
*/
|
|
|
|
err2 = omap_sham_final(req);
|
|
|
|
|
|
|
|
return err1 ?: err2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_digest(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
return omap_sham_init(req) ?: omap_sham_finup(req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
|
|
int bs = crypto_shash_blocksize(bctx->shash);
|
|
|
|
int ds = crypto_shash_digestsize(bctx->shash);
|
|
|
|
int err, i;
|
|
|
|
err = crypto_shash_setkey(tctx->fallback, key, keylen);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
if (keylen > bs) {
|
|
|
|
err = omap_sham_shash_digest(bctx->shash,
|
|
|
|
crypto_shash_get_flags(bctx->shash),
|
|
|
|
key, keylen, bctx->ipad);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
keylen = ds;
|
|
|
|
} else {
|
|
|
|
memcpy(bctx->ipad, key, keylen);
|
|
|
|
}
|
|
|
|
|
|
|
|
memset(bctx->ipad + keylen, 0, bs - keylen);
|
|
|
|
memcpy(bctx->opad, bctx->ipad, bs);
|
|
|
|
|
|
|
|
for (i = 0; i < bs; i++) {
|
|
|
|
bctx->ipad[i] ^= 0x36;
|
|
|
|
bctx->opad[i] ^= 0x5c;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
|
|
|
|
{
|
|
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
|
|
|
|
const char *alg_name = crypto_tfm_alg_name(tfm);
|
|
|
|
|
|
|
|
/* Allocate a fallback and abort if it failed. */
|
|
|
|
tctx->fallback = crypto_alloc_shash(alg_name, 0,
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK);
|
|
|
|
if (IS_ERR(tctx->fallback)) {
|
|
|
|
pr_err("omap-sham: fallback driver '%s' "
|
|
|
|
"could not be loaded.\n", alg_name);
|
|
|
|
return PTR_ERR(tctx->fallback);
|
|
|
|
}
|
|
|
|
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
2010-11-19 14:04:26 +00:00
|
|
|
sizeof(struct omap_sham_reqctx) + BUFLEN);
|
2010-05-03 03:10:59 +00:00
|
|
|
|
|
|
|
if (alg_base) {
|
|
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
2011-06-02 18:10:05 +00:00
|
|
|
tctx->flags |= BIT(FLAGS_HMAC);
|
2010-05-03 03:10:59 +00:00
|
|
|
bctx->shash = crypto_alloc_shash(alg_base, 0,
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK);
|
|
|
|
if (IS_ERR(bctx->shash)) {
|
|
|
|
pr_err("omap-sham: base driver '%s' "
|
|
|
|
"could not be loaded.\n", alg_base);
|
|
|
|
crypto_free_shash(tctx->fallback);
|
|
|
|
return PTR_ERR(bctx->shash);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return omap_sham_cra_init_alg(tfm, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return omap_sham_cra_init_alg(tfm, "sha1");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return omap_sham_cra_init_alg(tfm, "md5");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap_sham_cra_exit(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
|
|
|
|
|
|
|
|
crypto_free_shash(tctx->fallback);
|
|
|
|
tctx->fallback = NULL;
|
|
|
|
|
2011-06-02 18:10:05 +00:00
|
|
|
if (tctx->flags & BIT(FLAGS_HMAC)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
struct omap_sham_hmac_ctx *bctx = tctx->base;
|
|
|
|
crypto_free_shash(bctx->shash);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ahash_alg algs[] = {
|
|
|
|
{
|
|
|
|
.init = omap_sham_init,
|
|
|
|
.update = omap_sham_update,
|
|
|
|
.final = omap_sham_final,
|
|
|
|
.finup = omap_sham_finup,
|
|
|
|
.digest = omap_sham_digest,
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha1",
|
|
|
|
.cra_driver_name = "omap-sha1",
|
|
|
|
.cra_priority = 100,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx),
|
|
|
|
.cra_alignmask = 0,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_init = omap_sham_cra_init,
|
|
|
|
.cra_exit = omap_sham_cra_exit,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = omap_sham_init,
|
|
|
|
.update = omap_sham_update,
|
|
|
|
.final = omap_sham_final,
|
|
|
|
.finup = omap_sham_finup,
|
|
|
|
.digest = omap_sham_digest,
|
|
|
|
.halg.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "md5",
|
|
|
|
.cra_driver_name = "omap-md5",
|
|
|
|
.cra_priority = 100,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx),
|
2010-11-19 14:04:26 +00:00
|
|
|
.cra_alignmask = OMAP_ALIGN_MASK,
|
2010-05-03 03:10:59 +00:00
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_init = omap_sham_cra_init,
|
|
|
|
.cra_exit = omap_sham_cra_exit,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = omap_sham_init,
|
|
|
|
.update = omap_sham_update,
|
|
|
|
.final = omap_sham_final,
|
|
|
|
.finup = omap_sham_finup,
|
|
|
|
.digest = omap_sham_digest,
|
|
|
|
.setkey = omap_sham_setkey,
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha1)",
|
|
|
|
.cra_driver_name = "omap-hmac-sha1",
|
|
|
|
.cra_priority = 100,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
|
|
sizeof(struct omap_sham_hmac_ctx),
|
2010-11-19 14:04:26 +00:00
|
|
|
.cra_alignmask = OMAP_ALIGN_MASK,
|
2010-05-03 03:10:59 +00:00
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_init = omap_sham_cra_sha1_init,
|
|
|
|
.cra_exit = omap_sham_cra_exit,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = omap_sham_init,
|
|
|
|
.update = omap_sham_update,
|
|
|
|
.final = omap_sham_final,
|
|
|
|
.finup = omap_sham_finup,
|
|
|
|
.digest = omap_sham_digest,
|
|
|
|
.setkey = omap_sham_setkey,
|
|
|
|
.halg.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(md5)",
|
|
|
|
.cra_driver_name = "omap-hmac-md5",
|
|
|
|
.cra_priority = 100,
|
|
|
|
.cra_flags = CRYPTO_ALG_TYPE_AHASH |
|
|
|
|
CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct omap_sham_ctx) +
|
|
|
|
sizeof(struct omap_sham_hmac_ctx),
|
2010-11-19 14:04:26 +00:00
|
|
|
.cra_alignmask = OMAP_ALIGN_MASK,
|
2010-05-03 03:10:59 +00:00
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_init = omap_sham_cra_md5_init,
|
|
|
|
.cra_exit = omap_sham_cra_exit,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void omap_sham_done_task(unsigned long data)
|
|
|
|
{
|
|
|
|
struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
|
2010-11-19 14:04:24 +00:00
|
|
|
int ready = 0, err = 0;
|
2010-05-03 03:10:59 +00:00
|
|
|
|
2011-06-02 18:10:09 +00:00
|
|
|
if (!test_bit(FLAGS_BUSY, &dd->flags)) {
|
|
|
|
omap_sham_handle_queue(dd, NULL);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-06-02 18:10:07 +00:00
|
|
|
if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
|
2010-05-03 03:10:59 +00:00
|
|
|
ready = 1;
|
|
|
|
|
2011-06-02 18:10:06 +00:00
|
|
|
if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
omap_sham_update_dma_stop(dd);
|
2010-11-19 14:04:24 +00:00
|
|
|
if (!dd->err)
|
2010-11-19 14:04:29 +00:00
|
|
|
err = omap_sham_update_dma_start(dd);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
2010-11-19 14:04:24 +00:00
|
|
|
err = dd->err ? : err;
|
|
|
|
|
|
|
|
if (err != -EINPROGRESS && (ready || err)) {
|
|
|
|
dev_dbg(dd->dev, "update done: err: %d\n", err);
|
2010-05-03 03:10:59 +00:00
|
|
|
/* finish curent request */
|
2011-06-02 18:10:08 +00:00
|
|
|
omap_sham_finish_req(dd->req, err);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t omap_sham_irq(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct omap_sham_dev *dd = dev_id;
|
|
|
|
|
2011-06-02 18:10:07 +00:00
|
|
|
if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
|
2010-05-03 03:10:59 +00:00
|
|
|
/* final -> allow device to go to power-saving mode */
|
|
|
|
omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
|
|
|
|
|
|
|
|
omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
|
|
|
|
SHA_REG_CTRL_OUTPUT_READY);
|
|
|
|
omap_sham_read(dd, SHA_REG_CTRL);
|
|
|
|
|
2011-06-02 18:10:07 +00:00
|
|
|
set_bit(FLAGS_OUTPUT_READY, &dd->flags);
|
2010-11-19 14:04:24 +00:00
|
|
|
dd->err = 0;
|
2010-05-03 03:10:59 +00:00
|
|
|
tasklet_schedule(&dd->done_task);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
|
|
|
|
{
|
|
|
|
struct omap_sham_dev *dd = data;
|
|
|
|
|
2010-11-19 14:04:24 +00:00
|
|
|
if (ch_status != OMAP_DMA_BLOCK_IRQ) {
|
|
|
|
pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
|
|
|
|
dd->err = -EIO;
|
2011-06-02 18:10:06 +00:00
|
|
|
clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
|
2010-11-19 14:04:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
tasklet_schedule(&dd->done_task);
|
2010-05-03 03:10:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_sham_dma_init(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
dd->dma_lch = -1;
|
|
|
|
|
|
|
|
err = omap_request_dma(dd->dma, dev_name(dd->dev),
|
|
|
|
omap_sham_dma_callback, dd, &dd->dma_lch);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dd->dev, "Unable to request DMA channel\n");
|
|
|
|
return err;
|
|
|
|
}
|
2010-09-03 11:20:19 +00:00
|
|
|
|
2010-05-03 03:10:59 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
|
|
|
|
{
|
|
|
|
if (dd->dma_lch >= 0) {
|
|
|
|
omap_free_dma(dd->dma_lch);
|
|
|
|
dd->dma_lch = -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devinit omap_sham_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct omap_sham_dev *dd;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct resource *res;
|
|
|
|
int err, i, j;
|
|
|
|
|
|
|
|
dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
|
|
|
|
if (dd == NULL) {
|
|
|
|
dev_err(dev, "unable to alloc data struct.\n");
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto data_err;
|
|
|
|
}
|
|
|
|
dd->dev = dev;
|
|
|
|
platform_set_drvdata(pdev, dd);
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&dd->list);
|
|
|
|
spin_lock_init(&dd->lock);
|
|
|
|
tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
|
|
|
|
crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
|
|
|
|
|
|
|
|
dd->irq = -1;
|
|
|
|
|
|
|
|
/* Get the base address */
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "no MEM resource info\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto res_err;
|
|
|
|
}
|
|
|
|
dd->phys_base = res->start;
|
|
|
|
|
|
|
|
/* Get the DMA */
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "no DMA resource info\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto res_err;
|
|
|
|
}
|
|
|
|
dd->dma = res->start;
|
|
|
|
|
|
|
|
/* Get the IRQ */
|
|
|
|
dd->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (dd->irq < 0) {
|
|
|
|
dev_err(dev, "no IRQ resource info\n");
|
|
|
|
err = dd->irq;
|
|
|
|
goto res_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = request_irq(dd->irq, omap_sham_irq,
|
|
|
|
IRQF_TRIGGER_LOW, dev_name(dev), dd);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "unable to request irq.\n");
|
|
|
|
goto res_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = omap_sham_dma_init(dd);
|
|
|
|
if (err)
|
|
|
|
goto dma_err;
|
|
|
|
|
|
|
|
/* Initializing the clock */
|
|
|
|
dd->iclk = clk_get(dev, "ick");
|
2011-01-29 05:01:02 +00:00
|
|
|
if (IS_ERR(dd->iclk)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
dev_err(dev, "clock intialization failed.\n");
|
2011-01-29 05:01:02 +00:00
|
|
|
err = PTR_ERR(dd->iclk);
|
2010-05-03 03:10:59 +00:00
|
|
|
goto clk_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
dd->io_base = ioremap(dd->phys_base, SZ_4K);
|
|
|
|
if (!dd->io_base) {
|
|
|
|
dev_err(dev, "can't ioremap\n");
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto io_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
clk_enable(dd->iclk);
|
|
|
|
dev_info(dev, "hw accel on OMAP rev %u.%u\n",
|
|
|
|
(omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
|
|
|
|
omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
|
|
|
|
clk_disable(dd->iclk);
|
|
|
|
|
|
|
|
spin_lock(&sham.lock);
|
|
|
|
list_add_tail(&dd->list, &sham.dev_list);
|
|
|
|
spin_unlock(&sham.lock);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(algs); i++) {
|
|
|
|
err = crypto_register_ahash(&algs[i]);
|
|
|
|
if (err)
|
|
|
|
goto err_algs;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_algs:
|
|
|
|
for (j = 0; j < i; j++)
|
|
|
|
crypto_unregister_ahash(&algs[j]);
|
|
|
|
iounmap(dd->io_base);
|
|
|
|
io_err:
|
|
|
|
clk_put(dd->iclk);
|
|
|
|
clk_err:
|
|
|
|
omap_sham_dma_cleanup(dd);
|
|
|
|
dma_err:
|
|
|
|
if (dd->irq >= 0)
|
|
|
|
free_irq(dd->irq, dd);
|
|
|
|
res_err:
|
|
|
|
kfree(dd);
|
|
|
|
dd = NULL;
|
|
|
|
data_err:
|
|
|
|
dev_err(dev, "initialization failed.\n");
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devexit omap_sham_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
static struct omap_sham_dev *dd;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dd = platform_get_drvdata(pdev);
|
|
|
|
if (!dd)
|
|
|
|
return -ENODEV;
|
|
|
|
spin_lock(&sham.lock);
|
|
|
|
list_del(&dd->list);
|
|
|
|
spin_unlock(&sham.lock);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(algs); i++)
|
|
|
|
crypto_unregister_ahash(&algs[i]);
|
|
|
|
tasklet_kill(&dd->done_task);
|
|
|
|
iounmap(dd->io_base);
|
|
|
|
clk_put(dd->iclk);
|
|
|
|
omap_sham_dma_cleanup(dd);
|
|
|
|
if (dd->irq >= 0)
|
|
|
|
free_irq(dd->irq, dd);
|
|
|
|
kfree(dd);
|
|
|
|
dd = NULL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver omap_sham_driver = {
|
|
|
|
.probe = omap_sham_probe,
|
|
|
|
.remove = omap_sham_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "omap-sham",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init omap_sham_mod_init(void)
|
|
|
|
{
|
|
|
|
pr_info("loading %s driver\n", "omap-sham");
|
|
|
|
|
|
|
|
if (!cpu_class_is_omap2() ||
|
2011-04-20 10:34:57 +00:00
|
|
|
(omap_type() != OMAP2_DEVICE_TYPE_SEC &&
|
|
|
|
omap_type() != OMAP2_DEVICE_TYPE_EMU)) {
|
2010-05-03 03:10:59 +00:00
|
|
|
pr_err("Unsupported cpu\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return platform_driver_register(&omap_sham_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit omap_sham_mod_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&omap_sham_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(omap_sham_mod_init);
|
|
|
|
module_exit(omap_sham_mod_exit);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Dmitry Kasatkin");
|