2010-04-01 11:30:58 +00:00
|
|
|
/*
|
|
|
|
* arch/arm/mach-spear3xx/spear310.c
|
|
|
|
*
|
|
|
|
* SPEAr310 machine source file
|
|
|
|
*
|
|
|
|
* Copyright (C) 2009 ST Microelectronics
|
|
|
|
* Viresh Kumar<viresh.kumar@st.com>
|
|
|
|
*
|
|
|
|
* This file is licensed under the terms of the GNU General Public
|
|
|
|
* License version 2. This program is licensed "as is" without any
|
|
|
|
* warranty of any kind, whether express or implied.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/ptrace.h>
|
|
|
|
#include <asm/irq.h>
|
2011-03-07 04:57:01 +00:00
|
|
|
#include <plat/shirq.h>
|
2010-04-01 11:30:58 +00:00
|
|
|
#include <mach/generic.h>
|
2011-03-07 04:57:02 +00:00
|
|
|
#include <mach/hardware.h>
|
2010-04-01 11:30:58 +00:00
|
|
|
|
2010-04-01 11:31:29 +00:00
|
|
|
/* pad multiplexing support */
|
|
|
|
/* muxing registers */
|
|
|
|
#define PAD_MUX_CONFIG_REG 0x08
|
|
|
|
|
|
|
|
/* devices */
|
|
|
|
struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_TIMER_3_4_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_emi_cs_0_1_4_5 = {
|
|
|
|
.name = "emi_cs_0_1_4_5",
|
|
|
|
.modes = pmx_emi_cs_0_1_4_5_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_TIMER_1_2_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_emi_cs_2_3 = {
|
|
|
|
.name = "emi_cs_2_3",
|
|
|
|
.modes = pmx_emi_cs_2_3_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_uart1_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_FIRDA_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_uart1 = {
|
|
|
|
.name = "uart1",
|
|
|
|
.modes = pmx_uart1_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_uart2_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_TIMER_1_2_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_uart2 = {
|
|
|
|
.name = "uart2",
|
|
|
|
.modes = pmx_uart2_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_UART0_MODEM_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_uart3_4_5 = {
|
|
|
|
.name = "uart3_4_5",
|
|
|
|
.modes = pmx_uart3_4_5_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_fsmc_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_SSP_CS_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_fsmc = {
|
|
|
|
.name = "fsmc",
|
|
|
|
.modes = pmx_fsmc_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_MII_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_rs485_0_1 = {
|
|
|
|
.name = "rs485_0_1",
|
|
|
|
.modes = pmx_rs485_0_1_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev_mode pmx_tdm0_modes[] = {
|
|
|
|
{
|
|
|
|
.ids = 0x00,
|
|
|
|
.mask = PMX_MII_MASK,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
struct pmx_dev pmx_tdm0 = {
|
|
|
|
.name = "tdm0",
|
|
|
|
.modes = pmx_tdm0_modes,
|
|
|
|
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
|
|
|
|
.enb_on_reset = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* pmx driver structure */
|
|
|
|
struct pmx_driver pmx_driver = {
|
|
|
|
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
|
|
|
|
};
|
|
|
|
|
2010-05-03 08:24:30 +00:00
|
|
|
/* spear3xx shared irq */
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct shirq_dev_config shirq_ras1_config[] = {
|
2010-05-03 08:24:30 +00:00
|
|
|
{
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_SMII0,
|
|
|
|
.status_mask = SPEAR310_SMII0_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_SMII1,
|
|
|
|
.status_mask = SPEAR310_SMII1_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_SMII2,
|
|
|
|
.status_mask = SPEAR310_SMII2_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_SMII3,
|
|
|
|
.status_mask = SPEAR310_SMII3_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_WAKEUP_SMII0,
|
|
|
|
.status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_WAKEUP_SMII1,
|
|
|
|
.status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_WAKEUP_SMII2,
|
|
|
|
.status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_WAKEUP_SMII3,
|
|
|
|
.status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct spear_shirq shirq_ras1 = {
|
2011-05-20 07:34:21 +00:00
|
|
|
.irq = SPEAR3XX_IRQ_GEN_RAS_1,
|
2010-05-03 08:24:30 +00:00
|
|
|
.dev_config = shirq_ras1_config,
|
|
|
|
.dev_count = ARRAY_SIZE(shirq_ras1_config),
|
|
|
|
.regs = {
|
|
|
|
.enb_reg = -1,
|
2011-05-20 07:34:21 +00:00
|
|
|
.status_reg = SPEAR310_INT_STS_MASK_REG,
|
|
|
|
.status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
.clear_reg = -1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct shirq_dev_config shirq_ras2_config[] = {
|
2010-05-03 08:24:30 +00:00
|
|
|
{
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_UART1,
|
|
|
|
.status_mask = SPEAR310_UART1_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_UART2,
|
|
|
|
.status_mask = SPEAR310_UART2_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_UART3,
|
|
|
|
.status_mask = SPEAR310_UART3_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_UART4,
|
|
|
|
.status_mask = SPEAR310_UART4_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_UART5,
|
|
|
|
.status_mask = SPEAR310_UART5_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct spear_shirq shirq_ras2 = {
|
2011-05-20 07:34:21 +00:00
|
|
|
.irq = SPEAR3XX_IRQ_GEN_RAS_2,
|
2010-05-03 08:24:30 +00:00
|
|
|
.dev_config = shirq_ras2_config,
|
|
|
|
.dev_count = ARRAY_SIZE(shirq_ras2_config),
|
|
|
|
.regs = {
|
|
|
|
.enb_reg = -1,
|
2011-05-20 07:34:21 +00:00
|
|
|
.status_reg = SPEAR310_INT_STS_MASK_REG,
|
|
|
|
.status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
.clear_reg = -1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct shirq_dev_config shirq_ras3_config[] = {
|
2010-05-03 08:24:30 +00:00
|
|
|
{
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_EMI,
|
|
|
|
.status_mask = SPEAR310_EMI_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct spear_shirq shirq_ras3 = {
|
2011-05-20 07:34:21 +00:00
|
|
|
.irq = SPEAR3XX_IRQ_GEN_RAS_3,
|
2010-05-03 08:24:30 +00:00
|
|
|
.dev_config = shirq_ras3_config,
|
|
|
|
.dev_count = ARRAY_SIZE(shirq_ras3_config),
|
|
|
|
.regs = {
|
|
|
|
.enb_reg = -1,
|
2011-05-20 07:34:21 +00:00
|
|
|
.status_reg = SPEAR310_INT_STS_MASK_REG,
|
|
|
|
.status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
.clear_reg = -1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
|
2010-05-03 08:24:30 +00:00
|
|
|
{
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_TDM_HDLC,
|
|
|
|
.status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_RS485_0,
|
|
|
|
.status_mask = SPEAR310_RS485_0_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
}, {
|
2011-05-20 07:34:21 +00:00
|
|
|
.virq = SPEAR310_VIRQ_RS485_1,
|
|
|
|
.status_mask = SPEAR310_RS485_1_IRQ_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-05-20 07:34:20 +00:00
|
|
|
static struct spear_shirq shirq_intrcomm_ras = {
|
2011-05-20 07:34:21 +00:00
|
|
|
.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
|
2010-05-03 08:24:30 +00:00
|
|
|
.dev_config = shirq_intrcomm_ras_config,
|
|
|
|
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
|
|
|
|
.regs = {
|
|
|
|
.enb_reg = -1,
|
2011-05-20 07:34:21 +00:00
|
|
|
.status_reg = SPEAR310_INT_STS_MASK_REG,
|
|
|
|
.status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
|
2010-05-03 08:24:30 +00:00
|
|
|
.clear_reg = -1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-03-07 04:57:05 +00:00
|
|
|
/* Add spear310 specific devices here */
|
|
|
|
|
2010-04-01 11:31:29 +00:00
|
|
|
/* spear310 routines */
|
2010-04-01 11:30:58 +00:00
|
|
|
void __init spear310_init(void)
|
|
|
|
{
|
2010-05-03 08:24:30 +00:00
|
|
|
void __iomem *base;
|
|
|
|
int ret = 0;
|
|
|
|
|
2010-04-01 11:30:58 +00:00
|
|
|
/* call spear3xx family common init function */
|
|
|
|
spear3xx_init();
|
2010-05-03 08:24:30 +00:00
|
|
|
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 19:38:34 +00:00
|
|
|
/* shared irq registration */
|
2011-03-07 04:57:06 +00:00
|
|
|
base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
|
2010-05-03 08:24:30 +00:00
|
|
|
if (base) {
|
|
|
|
/* shirq 1 */
|
|
|
|
shirq_ras1.regs.base = base;
|
|
|
|
ret = spear_shirq_register(&shirq_ras1);
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Error registering Shared IRQ 1\n");
|
|
|
|
|
|
|
|
/* shirq 2 */
|
|
|
|
shirq_ras2.regs.base = base;
|
|
|
|
ret = spear_shirq_register(&shirq_ras2);
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Error registering Shared IRQ 2\n");
|
|
|
|
|
|
|
|
/* shirq 3 */
|
|
|
|
shirq_ras3.regs.base = base;
|
|
|
|
ret = spear_shirq_register(&shirq_ras3);
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Error registering Shared IRQ 3\n");
|
|
|
|
|
|
|
|
/* shirq 4 */
|
|
|
|
shirq_intrcomm_ras.regs.base = base;
|
|
|
|
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Error registering Shared IRQ 4\n");
|
|
|
|
}
|
2010-04-01 11:31:29 +00:00
|
|
|
|
2011-02-16 06:40:30 +00:00
|
|
|
/* pmx initialization */
|
|
|
|
pmx_driver.base = base;
|
|
|
|
ret = pmx_register(&pmx_driver);
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
|
|
|
|
ret);
|
2010-04-01 11:31:29 +00:00
|
|
|
}
|