2007-09-26 00:57:13 +00:00
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/*
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2009-11-08 15:39:55 +00:00
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Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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2007-09-26 00:57:13 +00:00
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt2400pci
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Abstract: rt2400pci device specific routines.
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Supported chipsets: RT2460.
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/eeprom_93cx6.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2007-09-26 00:57:13 +00:00
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#include "rt2x00.h"
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#include "rt2x00pci.h"
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#include "rt2400pci.h"
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/*
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* Register access.
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* All access to the CSR registers will go through the methods
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* rt2x00pci_register_read and rt2x00pci_register_write.
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* BBP and RF register require indirect register access,
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* and use the CSR registers BBPCSR and RFCSR to achieve this.
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* These indirect registers work with busy bits,
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* and we will try maximal REGISTER_BUSY_COUNT times to access
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* the register while taking a REGISTER_BUSY_DELAY us delay
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2011-01-30 12:22:03 +00:00
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* between each attempt. When the busy bit is still set at that time,
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2007-09-26 00:57:13 +00:00
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* the access attempt is considered to have failed,
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* and we will print an error.
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*/
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2008-11-10 18:41:40 +00:00
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#define WAIT_FOR_BBP(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
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#define WAIT_FOR_RF(__dev, __reg) \
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rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
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2007-09-26 00:57:13 +00:00
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2007-10-27 11:41:25 +00:00
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static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
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2007-09-26 00:57:13 +00:00
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const unsigned int word, const u8 value)
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{
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u32 reg;
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2008-11-09 22:40:46 +00:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2007-09-26 00:57:13 +00:00
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/*
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2008-11-10 18:41:40 +00:00
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* Wait until the BBP becomes available, afterwards we
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* can safely write the new data into the register.
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2007-09-26 00:57:13 +00:00
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*/
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2008-11-10 18:41:40 +00:00
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if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, BBPCSR_VALUE, value);
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rt2x00_set_field32(®, BBPCSR_REGNUM, word);
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rt2x00_set_field32(®, BBPCSR_BUSY, 1);
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rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
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rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
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}
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2008-11-09 22:40:46 +00:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 00:57:13 +00:00
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}
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2007-10-27 11:41:25 +00:00
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static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
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2007-09-26 00:57:13 +00:00
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const unsigned int word, u8 *value)
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{
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u32 reg;
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2008-11-09 22:40:46 +00:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2007-09-26 00:57:13 +00:00
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/*
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2008-11-10 18:41:40 +00:00
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* Wait until the BBP becomes available, afterwards we
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* can safely write the read request into the register.
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* After the data has been written, we wait until hardware
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* returns the correct value, if at any time the register
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* doesn't become available in time, reg will be 0xffffffff
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* which means we return 0xff to the caller.
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2007-09-26 00:57:13 +00:00
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*/
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2008-11-10 18:41:40 +00:00
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if (WAIT_FOR_BBP(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, BBPCSR_REGNUM, word);
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rt2x00_set_field32(®, BBPCSR_BUSY, 1);
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rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
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2007-09-26 00:57:13 +00:00
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2008-11-10 18:41:40 +00:00
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rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
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2007-09-26 00:57:13 +00:00
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2008-11-10 18:41:40 +00:00
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WAIT_FOR_BBP(rt2x00dev, ®);
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}
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2007-09-26 00:57:13 +00:00
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*value = rt2x00_get_field32(reg, BBPCSR_VALUE);
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2008-11-09 22:40:46 +00:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 00:57:13 +00:00
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}
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2007-10-27 11:41:25 +00:00
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static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
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2007-09-26 00:57:13 +00:00
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const unsigned int word, const u32 value)
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{
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u32 reg;
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2008-11-09 22:40:46 +00:00
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mutex_lock(&rt2x00dev->csr_mutex);
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2008-11-10 18:41:40 +00:00
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/*
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* Wait until the RF becomes available, afterwards we
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* can safely write the new data into the register.
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*/
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if (WAIT_FOR_RF(rt2x00dev, ®)) {
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reg = 0;
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rt2x00_set_field32(®, RFCSR_VALUE, value);
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rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
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rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
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rt2x00_set_field32(®, RFCSR_BUSY, 1);
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rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
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rt2x00_rf_write(rt2x00dev, word, value);
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2007-09-26 00:57:13 +00:00
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}
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2008-11-09 22:40:46 +00:00
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mutex_unlock(&rt2x00dev->csr_mutex);
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2007-09-26 00:57:13 +00:00
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}
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static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, CSR21, ®);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
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eeprom->reg_data_clock =
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!!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
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eeprom->reg_chip_select =
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!!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
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}
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static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg = 0;
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rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
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rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
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rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK,
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!!eeprom->reg_data_clock);
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rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00pci_register_write(rt2x00dev, CSR21, reg);
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}
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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static const struct rt2x00debug rt2400pci_rt2x00debug = {
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.owner = THIS_MODULE,
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.csr = {
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2008-10-29 18:41:03 +00:00
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.read = rt2x00pci_register_read,
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.write = rt2x00pci_register_write,
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.flags = RT2X00DEBUGFS_OFFSET,
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.word_base = CSR_REG_BASE,
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2007-09-26 00:57:13 +00:00
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.word_size = sizeof(u32),
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.word_count = CSR_REG_SIZE / sizeof(u32),
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},
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.eeprom = {
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.read = rt2x00_eeprom_read,
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.write = rt2x00_eeprom_write,
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2008-10-29 18:41:03 +00:00
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.word_base = EEPROM_BASE,
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2007-09-26 00:57:13 +00:00
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.word_size = sizeof(u16),
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.word_count = EEPROM_SIZE / sizeof(u16),
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},
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.bbp = {
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.read = rt2400pci_bbp_read,
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.write = rt2400pci_bbp_write,
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2008-10-29 18:41:03 +00:00
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.word_base = BBP_BASE,
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2007-09-26 00:57:13 +00:00
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.word_size = sizeof(u8),
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.word_count = BBP_SIZE / sizeof(u8),
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},
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.rf = {
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.read = rt2x00_rf_read,
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.write = rt2400pci_rf_write,
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2008-10-29 18:41:03 +00:00
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.word_base = RF_BASE,
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2007-09-26 00:57:13 +00:00
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.word_size = sizeof(u32),
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.word_count = RF_SIZE / sizeof(u32),
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},
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};
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#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
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static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
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return rt2x00_get_field32(reg, GPIOCSR_BIT0);
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}
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2008-09-08 17:07:15 +00:00
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#ifdef CONFIG_RT2X00_LIB_LEDS
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2008-03-31 13:53:44 +00:00
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static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
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2008-02-03 14:53:40 +00:00
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enum led_brightness brightness)
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{
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struct rt2x00_led *led =
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container_of(led_cdev, struct rt2x00_led, led_dev);
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unsigned int enabled = brightness != LED_OFF;
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u32 reg;
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rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
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2008-03-31 13:53:44 +00:00
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if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
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2008-02-03 14:53:40 +00:00
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rt2x00_set_field32(®, LEDCSR_LINK, enabled);
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2008-03-31 13:53:44 +00:00
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else if (led->type == LED_TYPE_ACTIVITY)
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rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled);
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2008-02-03 14:53:40 +00:00
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rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
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}
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2008-03-31 13:53:44 +00:00
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static int rt2400pci_blink_set(struct led_classdev *led_cdev,
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unsigned long *delay_on,
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unsigned long *delay_off)
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{
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struct rt2x00_led *led =
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container_of(led_cdev, struct rt2x00_led, led_dev);
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u32 reg;
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rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®);
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rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on);
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rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off);
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rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
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return 0;
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}
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2008-06-03 18:30:01 +00:00
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static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
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struct rt2x00_led *led,
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enum led_type type)
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{
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led->rt2x00dev = rt2x00dev;
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led->type = type;
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led->led_dev.brightness_set = rt2400pci_brightness_set;
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led->led_dev.blink_set = rt2400pci_blink_set;
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led->flags = LED_INITIALIZED;
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}
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2008-09-08 17:07:15 +00:00
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|
|
#endif /* CONFIG_RT2X00_LIB_LEDS */
|
2008-02-03 14:53:40 +00:00
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* Configuration handlers.
|
|
|
|
*/
|
2008-03-25 13:13:18 +00:00
|
|
|
static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
|
|
|
|
const unsigned int filter_flags)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start configuration steps.
|
|
|
|
* Note that the version error will always be dropped
|
|
|
|
* since there is no filter for it at this time.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_CRC,
|
|
|
|
!(filter_flags & FIF_FCSFAIL));
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL,
|
|
|
|
!(filter_flags & FIF_PLCPFAIL));
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_CONTROL,
|
|
|
|
!(filter_flags & FIF_CONTROL));
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME,
|
|
|
|
!(filter_flags & FIF_PROMISC_IN_BSS));
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_TODS,
|
2008-03-31 13:24:53 +00:00
|
|
|
!(filter_flags & FIF_PROMISC_IN_BSS) &&
|
|
|
|
!rt2x00dev->intf_ap_count);
|
2008-03-25 13:13:18 +00:00
|
|
|
rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
|
|
|
|
}
|
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00_intf *intf,
|
|
|
|
struct rt2x00intf_conf *conf,
|
|
|
|
const unsigned int flags)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
unsigned int bcn_preload;
|
|
|
|
u32 reg;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
if (flags & CONFIG_UPDATE_TYPE) {
|
|
|
|
/*
|
|
|
|
* Enable beacon config
|
|
|
|
*/
|
2008-11-09 19:47:00 +00:00
|
|
|
bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
|
|
|
|
rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
/*
|
|
|
|
* Enable synchronisation.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
|
|
|
rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
if (flags & CONFIG_UPDATE_MAC)
|
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
|
|
|
|
conf->mac, sizeof(conf->mac));
|
2007-09-26 00:57:13 +00:00
|
|
|
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
if (flags & CONFIG_UPDATE_BSSID)
|
|
|
|
rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
|
|
|
|
conf->bssid, sizeof(conf->bssid));
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-03-25 13:13:18 +00:00
|
|
|
static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
|
2010-09-08 18:56:32 +00:00
|
|
|
struct rt2x00lib_erp *erp,
|
|
|
|
u32 changed)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2007-10-06 11:34:52 +00:00
|
|
|
int preamble_mask;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 reg;
|
|
|
|
|
2007-10-06 11:34:52 +00:00
|
|
|
/*
|
|
|
|
* When short preamble is enabled, we should set bit 0x08
|
|
|
|
*/
|
2010-09-08 18:56:32 +00:00
|
|
|
if (changed & BSS_CHANGED_ERP_PREAMBLE) {
|
|
|
|
preamble_mask = erp->short_preamble << 3;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
|
|
|
|
rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff);
|
|
|
|
rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a);
|
|
|
|
rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
|
|
|
|
rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_LENGTH,
|
|
|
|
GET_DURATION(ACK_SIZE, 10));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
|
|
|
|
rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
|
|
|
|
rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_LENGTH,
|
|
|
|
GET_DURATION(ACK_SIZE, 20));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
|
|
|
|
rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
|
|
|
|
rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_LENGTH,
|
|
|
|
GET_DURATION(ACK_SIZE, 55));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
|
|
|
|
rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
|
|
|
|
rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
|
|
|
|
rt2x00_set_field32(®, ARCSR2_LENGTH,
|
|
|
|
GET_DURATION(ACK_SIZE, 110));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (changed & BSS_CHANGED_BASIC_RATES)
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
|
|
|
|
|
|
|
|
if (changed & BSS_CHANGED_ERP_SLOT) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
|
|
|
|
rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR18, ®);
|
|
|
|
rt2x00_set_field32(®, CSR18_SIFS, erp->sifs);
|
|
|
|
rt2x00_set_field32(®, CSR18_PIFS, erp->pifs);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR18, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR19, ®);
|
|
|
|
rt2x00_set_field32(®, CSR19_DIFS, erp->difs);
|
|
|
|
rt2x00_set_field32(®, CSR19_EIFS, erp->eifs);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR19, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (changed & BSS_CHANGED_BEACON_INT) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR12, ®);
|
|
|
|
rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
|
|
|
|
erp->beacon_int * 16);
|
|
|
|
rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
|
|
|
|
erp->beacon_int * 16);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR12, reg);
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-10-29 16:17:57 +00:00
|
|
|
static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct antenna_setup *ant)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-10-29 16:17:57 +00:00
|
|
|
u8 r1;
|
|
|
|
u8 r4;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We should never come here because rt2x00lib is supposed
|
|
|
|
* to catch this and send us the correct antenna explicitely.
|
|
|
|
*/
|
|
|
|
BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
|
|
|
|
ant->tx == ANTENNA_SW_DIVERSITY);
|
|
|
|
|
|
|
|
rt2400pci_bbp_read(rt2x00dev, 4, &r4);
|
|
|
|
rt2400pci_bbp_read(rt2x00dev, 1, &r1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the TX antenna.
|
|
|
|
*/
|
|
|
|
switch (ant->tx) {
|
|
|
|
case ANTENNA_HW_DIVERSITY:
|
|
|
|
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
|
|
|
|
break;
|
|
|
|
case ANTENNA_A:
|
|
|
|
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
|
|
|
|
break;
|
|
|
|
case ANTENNA_B:
|
|
|
|
default:
|
|
|
|
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the RX antenna.
|
|
|
|
*/
|
|
|
|
switch (ant->rx) {
|
|
|
|
case ANTENNA_HW_DIVERSITY:
|
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
|
|
|
|
break;
|
|
|
|
case ANTENNA_A:
|
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
|
|
|
|
break;
|
|
|
|
case ANTENNA_B:
|
|
|
|
default:
|
|
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 4, r4);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 1, r1);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
|
2007-10-06 11:34:52 +00:00
|
|
|
struct rf_channel *rf)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Switch on tuning bits.
|
|
|
|
*/
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
|
|
|
|
rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
|
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* RF2420 chipset don't need any additional actions.
|
|
|
|
*/
|
2009-12-22 23:03:25 +00:00
|
|
|
if (rt2x00_rf(rt2x00dev, RF2420))
|
2007-09-26 00:57:13 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For the RT2421 chipsets we need to write an invalid
|
|
|
|
* reference clock rate to activate auto_tune.
|
|
|
|
* After that we set the value back to the correct channel.
|
|
|
|
*/
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
msleep(1);
|
|
|
|
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
|
|
|
|
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
msleep(1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Switch off tuning bits.
|
|
|
|
*/
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
|
|
|
|
rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
|
|
|
|
rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear false CRC during channel switch.
|
|
|
|
*/
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
|
|
|
|
{
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
|
|
|
|
}
|
|
|
|
|
2008-10-29 16:17:57 +00:00
|
|
|
static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00lib_conf *libconf)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-10-29 16:17:57 +00:00
|
|
|
u32 reg;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-10-29 16:17:57 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
|
|
|
|
rt2x00_set_field32(®, CSR11_LONG_RETRY,
|
|
|
|
libconf->conf->long_frame_max_tx_count);
|
|
|
|
rt2x00_set_field32(®, CSR11_SHORT_RETRY,
|
|
|
|
libconf->conf->short_frame_max_tx_count);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-12-20 09:52:42 +00:00
|
|
|
static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00lib_conf *libconf)
|
|
|
|
{
|
|
|
|
enum dev_state state =
|
|
|
|
(libconf->conf->flags & IEEE80211_CONF_PS) ?
|
|
|
|
STATE_SLEEP : STATE_AWAKE;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
if (state == STATE_SLEEP) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR20, ®);
|
|
|
|
rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN,
|
2009-05-23 19:09:28 +00:00
|
|
|
(rt2x00dev->beacon_int - 20) * 16);
|
2008-12-20 09:52:42 +00:00
|
|
|
rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP,
|
|
|
|
libconf->conf->listen_interval - 1);
|
|
|
|
|
|
|
|
/* We must first disable autowake before it can be enabled */
|
|
|
|
rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR20, reg);
|
|
|
|
|
|
|
|
rt2x00_set_field32(®, CSR20_AUTOWAKE, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR20, reg);
|
2010-03-30 21:50:23 +00:00
|
|
|
} else {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR20, ®);
|
|
|
|
rt2x00_set_field32(®, CSR20_AUTOWAKE, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR20, reg);
|
2008-12-20 09:52:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
|
|
|
|
}
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
struct rt2x00lib_conf *libconf,
|
|
|
|
const unsigned int flags)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-10-29 16:17:57 +00:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_config_channel(rt2x00dev, &libconf->rf);
|
2008-10-29 16:17:57 +00:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_POWER)
|
2007-10-06 11:34:52 +00:00
|
|
|
rt2400pci_config_txpower(rt2x00dev,
|
|
|
|
libconf->conf->power_level);
|
2008-10-29 16:17:57 +00:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
|
|
|
|
rt2400pci_config_retry_limit(rt2x00dev, libconf);
|
2008-12-20 09:52:42 +00:00
|
|
|
if (flags & IEEE80211_CONF_CHANGE_PS)
|
|
|
|
rt2400pci_config_ps(rt2x00dev, libconf);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
|
2008-02-05 21:42:23 +00:00
|
|
|
const int cw_min, const int cw_max)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
|
2008-02-05 21:42:23 +00:00
|
|
|
rt2x00_set_field32(®, CSR11_CWMIN, cw_min);
|
|
|
|
rt2x00_set_field32(®, CSR11_CWMAX, cw_max);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Link tuning
|
|
|
|
*/
|
2007-10-13 14:26:12 +00:00
|
|
|
static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u8 bbp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update FCS error count from register.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
|
2007-10-13 14:26:12 +00:00
|
|
|
qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Update False CCA count from register.
|
|
|
|
*/
|
|
|
|
rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
|
2007-10-13 14:26:12 +00:00
|
|
|
qual->false_cca = bbp;
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-12-20 09:54:54 +00:00
|
|
|
static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual, u8 vgc_level)
|
2008-12-20 09:54:22 +00:00
|
|
|
{
|
2010-07-11 10:25:17 +00:00
|
|
|
if (qual->vgc_level_reg != vgc_level) {
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
|
|
|
|
qual->vgc_level = vgc_level;
|
|
|
|
qual->vgc_level_reg = vgc_level;
|
|
|
|
}
|
2008-12-20 09:54:22 +00:00
|
|
|
}
|
|
|
|
|
2008-12-20 09:54:54 +00:00
|
|
|
static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-12-20 09:54:54 +00:00
|
|
|
rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-12-20 09:54:54 +00:00
|
|
|
static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct link_qual *qual, const u32 count)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* The link tuner should not run longer then 60 seconds,
|
|
|
|
* and should run once every 2 seconds.
|
|
|
|
*/
|
2008-12-20 09:54:54 +00:00
|
|
|
if (count > 60 || !(count & 1))
|
2007-09-26 00:57:13 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Base r13 link tuning on the false cca count.
|
|
|
|
*/
|
2008-12-20 09:54:54 +00:00
|
|
|
if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
|
|
|
|
rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
|
|
|
|
else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
|
|
|
|
rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2010-12-13 11:34:22 +00:00
|
|
|
/*
|
|
|
|
* Queue handlers.
|
|
|
|
*/
|
|
|
|
static void rt2400pci_start_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
|
|
|
case QID_RX:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_BEACON:
|
2011-01-30 12:20:05 +00:00
|
|
|
/*
|
|
|
|
* Allow the tbtt tasklet to be scheduled.
|
|
|
|
*/
|
|
|
|
tasklet_enable(&rt2x00dev->tbtt_tasklet);
|
|
|
|
|
2010-12-13 11:34:22 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
|
|
|
rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
|
|
|
|
rt2x00_set_field32(®, CSR14_TBCN, 1);
|
|
|
|
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_kick_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
2010-12-13 11:36:38 +00:00
|
|
|
case QID_AC_VO:
|
2010-12-13 11:34:22 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
|
|
|
break;
|
2010-12-13 11:36:38 +00:00
|
|
|
case QID_AC_VI:
|
2010-12-13 11:34:22 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_ATIM:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_stop_queue(struct data_queue *queue)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
switch (queue->qid) {
|
2010-12-13 11:36:38 +00:00
|
|
|
case QID_AC_VO:
|
|
|
|
case QID_AC_VI:
|
2010-12-13 11:34:22 +00:00
|
|
|
case QID_ATIM:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, TXCSR0_ABORT, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_RX:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
|
|
|
|
break;
|
|
|
|
case QID_BEACON:
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
|
|
|
rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TBCN, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
2011-01-30 12:20:05 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for possibly running tbtt tasklets.
|
|
|
|
*/
|
|
|
|
tasklet_disable(&rt2x00dev->tbtt_tasklet);
|
2010-12-13 11:34:22 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* Initialization functions.
|
|
|
|
*/
|
2008-11-08 14:25:33 +00:00
|
|
|
static bool rt2400pci_get_entry_state(struct queue_entry *entry)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-05-10 11:46:03 +00:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 word;
|
|
|
|
|
2008-11-08 14:25:33 +00:00
|
|
|
if (entry->queue->qid == QID_RX) {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-11-08 14:25:33 +00:00
|
|
|
return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
|
|
|
|
} else {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-11-08 14:25:33 +00:00
|
|
|
return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
|
|
|
|
rt2x00_get_field32(word, TXD_W0_VALID));
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-11-08 14:25:33 +00:00
|
|
|
static void rt2400pci_clear_entry(struct queue_entry *entry)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-05-10 11:46:03 +00:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2008-11-08 14:25:33 +00:00
|
|
|
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 word;
|
|
|
|
|
2008-11-08 14:25:33 +00:00
|
|
|
if (entry->queue->qid == QID_RX) {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 2, &word);
|
|
|
|
rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 2, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 1, &word);
|
|
|
|
rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 1, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 0, word);
|
|
|
|
} else {
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_VALID, 0);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
|
|
|
|
rt2x00_desc_write(entry_priv->desc, 0, word);
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2008-02-05 21:42:23 +00:00
|
|
|
static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-05-10 11:46:03 +00:00
|
|
|
struct queue_entry_priv_pci *entry_priv;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize registers.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR2, ®);
|
2008-02-05 21:42:23 +00:00
|
|
|
rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
|
|
|
|
rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
|
|
|
|
rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
|
|
|
|
rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
|
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR3, ®);
|
2008-02-17 16:33:24 +00:00
|
|
|
rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER,
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
|
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR5, ®);
|
2008-02-17 16:33:24 +00:00
|
|
|
rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER,
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
|
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR4, ®);
|
2008-02-17 16:33:24 +00:00
|
|
|
rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER,
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
|
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, TXCSR6, ®);
|
2008-02-17 16:33:24 +00:00
|
|
|
rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER,
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv->desc_dma);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR1, ®);
|
|
|
|
rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
|
2008-02-05 21:42:23 +00:00
|
|
|
rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
|
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = rt2x00dev->rx->entries[0].priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR2, ®);
|
2008-05-10 11:46:03 +00:00
|
|
|
rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER,
|
|
|
|
entry_priv->desc_dma);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, TIMECSR, ®);
|
|
|
|
rt2x00_set_field32(®, TIMECSR_US_COUNT, 33);
|
|
|
|
rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63);
|
|
|
|
rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR9, ®);
|
|
|
|
rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT,
|
|
|
|
(rt2x00dev->rx->data_size / 128));
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR9, reg);
|
|
|
|
|
2008-07-08 11:45:20 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
|
|
|
rt2x00_set_field32(®, CSR14_TSF_COUNT, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TBCN, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TCFP, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TATIMW, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0);
|
|
|
|
rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, ARCSR0, ®);
|
|
|
|
rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133);
|
|
|
|
rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134);
|
|
|
|
rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136);
|
|
|
|
rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RXCSR3, ®);
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1);
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */
|
|
|
|
rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
|
|
|
|
|
|
|
|
if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, MACCSR2, ®);
|
|
|
|
rt2x00_set_field32(®, MACCSR2_DELAY, 64);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®);
|
|
|
|
rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17);
|
|
|
|
rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154);
|
|
|
|
rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0);
|
|
|
|
rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, CSR1_SOFT_RESET, 1);
|
|
|
|
rt2x00_set_field32(®, CSR1_BBP_RESET, 0);
|
|
|
|
rt2x00_set_field32(®, CSR1_HOST_READY, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR1, reg);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR1, ®);
|
|
|
|
rt2x00_set_field32(®, CSR1_SOFT_RESET, 0);
|
|
|
|
rt2x00_set_field32(®, CSR1_HOST_READY, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR1, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We must clear the FCS and FIFO error count.
|
|
|
|
* These registers are cleared on read,
|
|
|
|
* so we may pass a useless variable to store the value.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CNT4, ®);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-06-03 16:58:56 +00:00
|
|
|
static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
u8 value;
|
|
|
|
|
|
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
|
|
rt2400pci_bbp_read(rt2x00dev, 0, &value);
|
|
|
|
if ((value != 0xff) && (value != 0x00))
|
2008-06-03 16:58:56 +00:00
|
|
|
return 0;
|
2007-09-26 00:57:13 +00:00
|
|
|
udelay(REGISTER_BUSY_DELAY);
|
|
|
|
}
|
|
|
|
|
|
|
|
ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
|
|
|
|
return -EACCES;
|
2008-06-03 16:58:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
u16 eeprom;
|
|
|
|
u8 reg_id;
|
|
|
|
u8 value;
|
|
|
|
|
|
|
|
if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
|
|
|
|
return -EACCES;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
|
|
|
|
|
|
|
|
for (i = 0; i < EEPROM_BBP_SIZE; i++) {
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
|
|
|
|
|
|
|
|
if (eeprom != 0xffff && eeprom != 0x0000) {
|
|
|
|
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
|
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
|
|
|
|
rt2400pci_bbp_write(rt2x00dev, reg_id, value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device state switch handlers.
|
|
|
|
*/
|
|
|
|
static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
|
|
|
|
enum dev_state state)
|
|
|
|
{
|
2011-01-30 12:20:52 +00:00
|
|
|
int mask = (state == STATE_RADIO_IRQ_OFF);
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 reg;
|
2011-01-30 12:20:05 +00:00
|
|
|
unsigned long flags;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When interrupts are being enabled, the interrupt registers
|
|
|
|
* should clear the register to assure a clean state.
|
|
|
|
*/
|
|
|
|
if (state == STATE_RADIO_IRQ_ON) {
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
|
2011-01-30 12:20:05 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable tasklets.
|
|
|
|
*/
|
|
|
|
tasklet_enable(&rt2x00dev->txstatus_tasklet);
|
|
|
|
tasklet_enable(&rt2x00dev->rxdone_tasklet);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only toggle the interrupts bits we are going to use.
|
|
|
|
* Non-checked interrupt bits are disabled by default.
|
|
|
|
*/
|
2011-01-30 12:20:05 +00:00
|
|
|
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
|
|
|
rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask);
|
|
|
|
rt2x00_set_field32(®, CSR8_RXDONE, mask);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
2011-01-30 12:20:05 +00:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
|
|
|
|
if (state == STATE_RADIO_IRQ_OFF) {
|
|
|
|
/*
|
|
|
|
* Ensure that all tasklets are finished before
|
|
|
|
* disabling the interrupts.
|
|
|
|
*/
|
|
|
|
tasklet_disable(&rt2x00dev->txstatus_tasklet);
|
|
|
|
tasklet_disable(&rt2x00dev->rxdone_tasklet);
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Initialize all registers.
|
|
|
|
*/
|
2008-06-03 16:58:56 +00:00
|
|
|
if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
|
|
|
|
rt2400pci_init_registers(rt2x00dev) ||
|
|
|
|
rt2400pci_init_bbp(rt2x00dev)))
|
2007-09-26 00:57:13 +00:00
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
/*
|
2009-01-27 23:32:33 +00:00
|
|
|
* Disable power
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2009-01-27 23:32:33 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
|
|
|
|
enum dev_state state)
|
|
|
|
{
|
2010-05-13 19:16:03 +00:00
|
|
|
u32 reg, reg2;
|
2007-09-26 00:57:13 +00:00
|
|
|
unsigned int i;
|
|
|
|
char put_to_sleep;
|
|
|
|
char bbp_state;
|
|
|
|
char rf_state;
|
|
|
|
|
|
|
|
put_to_sleep = (state != STATE_AWAKE);
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®);
|
|
|
|
rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1);
|
|
|
|
rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state);
|
|
|
|
rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state);
|
|
|
|
rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Device is not guaranteed to be in the requested state yet.
|
|
|
|
* We must wait until the register indicates that the
|
|
|
|
* device has entered the correct state.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
2010-05-13 19:16:03 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2);
|
|
|
|
bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
|
|
|
|
rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
|
2007-09-26 00:57:13 +00:00
|
|
|
if (bbp_state == state && rf_state == state)
|
|
|
|
return 0;
|
2010-05-13 19:16:03 +00:00
|
|
|
rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
|
2007-09-26 00:57:13 +00:00
|
|
|
msleep(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|
|
|
enum dev_state state)
|
|
|
|
{
|
|
|
|
int retval = 0;
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
case STATE_RADIO_ON:
|
|
|
|
retval = rt2400pci_enable_radio(rt2x00dev);
|
|
|
|
break;
|
|
|
|
case STATE_RADIO_OFF:
|
|
|
|
rt2400pci_disable_radio(rt2x00dev);
|
|
|
|
break;
|
2008-06-03 16:58:56 +00:00
|
|
|
case STATE_RADIO_IRQ_ON:
|
|
|
|
case STATE_RADIO_IRQ_OFF:
|
|
|
|
rt2400pci_toggle_irq(rt2x00dev, state);
|
2007-09-26 00:57:13 +00:00
|
|
|
break;
|
|
|
|
case STATE_DEEP_SLEEP:
|
|
|
|
case STATE_SLEEP:
|
|
|
|
case STATE_STANDBY:
|
|
|
|
case STATE_AWAKE:
|
|
|
|
retval = rt2400pci_set_state(rt2x00dev, state);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retval = -ENOTSUPP;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-06-03 16:58:56 +00:00
|
|
|
if (unlikely(retval))
|
|
|
|
ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
|
|
|
|
state, retval);
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TX descriptor initialization
|
|
|
|
*/
|
2010-08-23 17:53:39 +00:00
|
|
|
static void rt2400pci_write_tx_desc(struct queue_entry *entry,
|
2008-05-10 11:42:31 +00:00
|
|
|
struct txentry_desc *txdesc)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2010-08-23 17:53:39 +00:00
|
|
|
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2010-05-11 21:51:40 +00:00
|
|
|
__le32 *txd = entry_priv->desc;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 word;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start writing the descriptor words.
|
|
|
|
*/
|
2010-05-11 21:51:40 +00:00
|
|
|
rt2x00_desc_read(txd, 1, &word);
|
2008-06-16 17:56:31 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
|
2010-05-11 21:51:40 +00:00
|
|
|
rt2x00_desc_write(txd, 1, word);
|
2008-05-10 11:44:14 +00:00
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_read(txd, 2, &word);
|
2010-05-03 20:43:05 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
|
|
|
|
rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_write(txd, 2, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(txd, 3, &word);
|
2011-03-03 18:42:35 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
|
2007-11-27 20:47:56 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
|
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
|
2011-03-03 18:42:35 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
|
2007-11-27 20:47:56 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
|
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_write(txd, 3, word);
|
|
|
|
|
|
|
|
rt2x00_desc_read(txd, 4, &word);
|
2011-03-03 18:42:35 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
|
|
|
|
txdesc->u.plcp.length_low);
|
2007-11-27 20:47:56 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
|
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
|
2011-03-03 18:42:35 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
|
|
|
|
txdesc->u.plcp.length_high);
|
2007-11-27 20:47:56 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
|
|
|
|
rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_write(txd, 4, word);
|
|
|
|
|
2010-05-11 21:51:39 +00:00
|
|
|
/*
|
|
|
|
* Writing TXD word 0 must the last to prevent a race condition with
|
|
|
|
* the device, whereby the device may take hold of the TXD before we
|
|
|
|
* finished updating it.
|
|
|
|
*/
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_read(txd, 0, &word);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_VALID, 1);
|
|
|
|
rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
|
2008-02-05 21:42:23 +00:00
|
|
|
test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_ACK,
|
2008-02-05 21:42:23 +00:00
|
|
|
test_bit(ENTRY_TXD_ACK, &txdesc->flags));
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
|
2008-02-05 21:42:23 +00:00
|
|
|
test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_RTS,
|
2008-02-05 21:42:23 +00:00
|
|
|
test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
|
2011-03-03 18:43:25 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
|
2008-05-10 11:45:58 +00:00
|
|
|
test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_desc_write(txd, 0, word);
|
2010-05-11 21:51:40 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Register descriptor details in skb frame descriptor.
|
|
|
|
*/
|
|
|
|
skbdesc->desc = txd;
|
|
|
|
skbdesc->desc_len = TXD_DESC_SIZE;
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TX data initialization
|
|
|
|
*/
|
2010-05-08 21:40:25 +00:00
|
|
|
static void rt2400pci_write_beacon(struct queue_entry *entry,
|
|
|
|
struct txentry_desc *txdesc)
|
2008-07-09 13:12:44 +00:00
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable beaconing while we are reloading the beacon data,
|
|
|
|
* otherwise we might be sending out invalid data.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR14, ®);
|
|
|
|
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
|
|
|
|
2010-10-11 13:37:25 +00:00
|
|
|
rt2x00queue_map_txskb(entry);
|
2008-07-09 13:12:44 +00:00
|
|
|
|
2010-06-03 08:51:41 +00:00
|
|
|
/*
|
|
|
|
* Write the TX descriptor for the beacon.
|
|
|
|
*/
|
2010-08-23 17:53:39 +00:00
|
|
|
rt2400pci_write_tx_desc(entry, txdesc);
|
2010-06-03 08:51:41 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Dump beacon to userspace through debugfs.
|
|
|
|
*/
|
|
|
|
rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
|
2010-05-08 21:40:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable beaconing again.
|
|
|
|
*/
|
|
|
|
rt2x00_set_field32(®, CSR14_BEACON_GEN, 1);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
|
2008-07-09 13:12:44 +00:00
|
|
|
}
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* RX control handlers
|
|
|
|
*/
|
2008-02-05 21:42:23 +00:00
|
|
|
static void rt2400pci_fill_rxdone(struct queue_entry *entry,
|
|
|
|
struct rxdone_entry_desc *rxdesc)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-07-04 14:14:59 +00:00
|
|
|
struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
|
2008-05-10 11:46:03 +00:00
|
|
|
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 word0;
|
|
|
|
u32 word2;
|
2008-03-09 21:49:04 +00:00
|
|
|
u32 word3;
|
2008-07-04 14:14:59 +00:00
|
|
|
u32 word4;
|
|
|
|
u64 tsf;
|
|
|
|
u32 rx_low;
|
|
|
|
u32 rx_high;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-05-10 11:46:03 +00:00
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word0);
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 2, &word2);
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 3, &word3);
|
2008-07-04 14:14:59 +00:00
|
|
|
rt2x00_desc_read(entry_priv->desc, 4, &word4);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
[PATCH] mac80211: revamp interface and filter configuration
Drivers are currently supposed to keep track of monitor
interfaces if they allow so-called "hard" monitor, and
they are also supposed to keep track of multicast etc.
This patch changes that, replaces the set_multicast_list()
callback with a new configure_filter() callback that takes
filter flags (FIF_*) instead of interface flags (IFF_*).
For a driver, this means it should open the filter as much
as necessary to get all frames requested by the filter flags.
Accordingly, the filter flags are named "positively", e.g.
FIF_ALLMULTI.
Multicast filtering is a bit special in that drivers that
have no multicast address filters need to allow multicast
frames through when either the FIF_ALLMULTI flag is set or
when the mc_count value is positive.
At the same time, drivers are no longer notified about
monitor interfaces at all, this means they now need to
implement the start() and stop() callbacks and the new
change_filter_flags() callback. Also, the start()/stop()
ordering changed, start() is now called *before* any
add_interface() as it really should be, and stop() after
any remove_interface().
The patch also changes the behaviour of setting the bssid
to multicast for scanning when IEEE80211_HW_NO_PROBE_FILTERING
is set; the IEEE80211_HW_NO_PROBE_FILTERING flag is removed
and the filter flag FIF_BCN_PRBRESP_PROMISC introduced.
This is a lot more efficient for hardware like b43 that
supports it and other hardware can still set the BSSID
to all-ones.
Driver modifications by Johannes Berg (b43 & iwlwifi), Michael Wu
(rtl8187, adm8211, and p54), Larry Finger (b43legacy), and
Ivo van Doorn (rt2x00).
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-09-17 05:29:23 +00:00
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
|
2008-02-05 21:42:23 +00:00
|
|
|
rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
|
[PATCH] mac80211: revamp interface and filter configuration
Drivers are currently supposed to keep track of monitor
interfaces if they allow so-called "hard" monitor, and
they are also supposed to keep track of multicast etc.
This patch changes that, replaces the set_multicast_list()
callback with a new configure_filter() callback that takes
filter flags (FIF_*) instead of interface flags (IFF_*).
For a driver, this means it should open the filter as much
as necessary to get all frames requested by the filter flags.
Accordingly, the filter flags are named "positively", e.g.
FIF_ALLMULTI.
Multicast filtering is a bit special in that drivers that
have no multicast address filters need to allow multicast
frames through when either the FIF_ALLMULTI flag is set or
when the mc_count value is positive.
At the same time, drivers are no longer notified about
monitor interfaces at all, this means they now need to
implement the start() and stop() callbacks and the new
change_filter_flags() callback. Also, the start()/stop()
ordering changed, start() is now called *before* any
add_interface() as it really should be, and stop() after
any remove_interface().
The patch also changes the behaviour of setting the bssid
to multicast for scanning when IEEE80211_HW_NO_PROBE_FILTERING
is set; the IEEE80211_HW_NO_PROBE_FILTERING flag is removed
and the filter flag FIF_BCN_PRBRESP_PROMISC introduced.
This is a lot more efficient for hardware like b43 that
supports it and other hardware can still set the BSSID
to all-ones.
Driver modifications by Johannes Berg (b43 & iwlwifi), Michael Wu
(rtl8187, adm8211, and p54), Larry Finger (b43legacy), and
Ivo van Doorn (rt2x00).
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-09-17 05:29:23 +00:00
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
|
2008-02-05 21:42:23 +00:00
|
|
|
rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-07-04 14:14:59 +00:00
|
|
|
/*
|
|
|
|
* We only get the lower 32bits from the timestamp,
|
|
|
|
* to get the full 64bits we must complement it with
|
|
|
|
* the timestamp from get_tsf().
|
|
|
|
* Note that when a wraparound of the lower 32bits
|
|
|
|
* has occurred between the frame arrival and the get_tsf()
|
|
|
|
* call, we must decrease the higher 32bits with 1 to get
|
|
|
|
* to correct value.
|
|
|
|
*/
|
|
|
|
tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
|
|
|
|
rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
|
|
|
|
rx_high = upper_32_bits(tsf);
|
|
|
|
|
|
|
|
if ((u32)tsf <= rx_low)
|
|
|
|
rx_high--;
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* Obtain the status about this packet.
|
2008-03-09 23:30:44 +00:00
|
|
|
* The signal is the PLCP value, and needs to be stripped
|
|
|
|
* of the preamble bit (0x08).
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2008-07-04 14:14:59 +00:00
|
|
|
rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
|
2008-03-09 23:30:44 +00:00
|
|
|
rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
|
2008-03-09 21:49:04 +00:00
|
|
|
rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
|
2008-02-05 21:42:23 +00:00
|
|
|
entry->queue->rt2x00dev->rssi_offset;
|
|
|
|
rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
|
2008-03-15 20:38:07 +00:00
|
|
|
|
2008-05-10 11:46:08 +00:00
|
|
|
rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
|
2008-03-15 20:38:07 +00:00
|
|
|
if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
|
|
|
|
rxdesc->dev_flags |= RXDONE_MY_BSS;
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Interrupt functions.
|
|
|
|
*/
|
2008-02-05 21:42:23 +00:00
|
|
|
static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
|
2008-04-21 17:00:47 +00:00
|
|
|
const enum data_queue_qid queue_idx)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2008-02-05 21:42:23 +00:00
|
|
|
struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
|
2008-05-10 11:46:03 +00:00
|
|
|
struct queue_entry_priv_pci *entry_priv;
|
2008-02-05 21:42:23 +00:00
|
|
|
struct queue_entry *entry;
|
|
|
|
struct txdone_entry_desc txdesc;
|
2007-09-26 00:57:13 +00:00
|
|
|
u32 word;
|
|
|
|
|
2008-02-05 21:42:23 +00:00
|
|
|
while (!rt2x00queue_empty(queue)) {
|
|
|
|
entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
|
2008-05-10 11:46:03 +00:00
|
|
|
entry_priv = entry->priv_data;
|
|
|
|
rt2x00_desc_read(entry_priv->desc, 0, &word);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
|
|
|
|
!rt2x00_get_field32(word, TXD_W0_VALID))
|
|
|
|
break;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Obtain the status about this packet.
|
|
|
|
*/
|
2008-05-10 11:42:06 +00:00
|
|
|
txdesc.flags = 0;
|
|
|
|
switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
|
|
|
|
case 0: /* Success */
|
|
|
|
case 1: /* Success with retry */
|
|
|
|
__set_bit(TXDONE_SUCCESS, &txdesc.flags);
|
|
|
|
break;
|
|
|
|
case 2: /* Failure, excessive retries */
|
|
|
|
__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
|
|
|
|
/* Don't break, this is a failed frame! */
|
|
|
|
default: /* Failure */
|
|
|
|
__set_bit(TXDONE_FAILURE, &txdesc.flags);
|
|
|
|
}
|
2008-02-05 21:42:23 +00:00
|
|
|
txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2010-06-29 19:41:40 +00:00
|
|
|
rt2x00lib_txdone(entry, &txdesc);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
static void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
|
|
|
|
struct rt2x00_field32 irq_field)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
2011-01-30 12:20:05 +00:00
|
|
|
unsigned long flags;
|
|
|
|
u32 reg;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
2011-01-30 12:20:05 +00:00
|
|
|
* Enable a single interrupt. The interrupt mask register
|
|
|
|
* access needs locking.
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2011-01-30 12:20:05 +00:00
|
|
|
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
|
|
|
rt2x00_set_field32(®, irq_field, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
}
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
static void rt2400pci_txstatus_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
u32 reg;
|
|
|
|
unsigned long flags;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
2011-01-30 12:20:05 +00:00
|
|
|
* Handle all tx queues.
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2011-01-30 12:20:05 +00:00
|
|
|
rt2400pci_txdone(rt2x00dev, QID_ATIM);
|
|
|
|
rt2400pci_txdone(rt2x00dev, QID_AC_VO);
|
|
|
|
rt2400pci_txdone(rt2x00dev, QID_AC_VI);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
2011-01-30 12:20:05 +00:00
|
|
|
* Enable all TXDONE interrupts again.
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2011-01-30 12:20:05 +00:00
|
|
|
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0);
|
|
|
|
rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_tbtt_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
rt2x00lib_beacondone(rt2x00dev);
|
|
|
|
rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rt2400pci_rxdone_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
|
|
|
rt2x00pci_rxdone(rt2x00dev);
|
|
|
|
rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
2010-07-11 10:26:48 +00:00
|
|
|
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = dev_instance;
|
2011-01-30 12:20:05 +00:00
|
|
|
u32 reg, mask;
|
|
|
|
unsigned long flags;
|
2010-07-11 10:26:48 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the interrupt sources & saved to local variable.
|
|
|
|
* Write register value back to clear pending interrupts.
|
|
|
|
*/
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR7, ®);
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR7, reg);
|
|
|
|
|
|
|
|
if (!reg)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
mask = reg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Schedule tasklets for interrupt handling.
|
|
|
|
*/
|
|
|
|
if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
|
|
|
|
tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
|
|
|
|
|
|
|
|
if (rt2x00_get_field32(reg, CSR7_RXDONE))
|
|
|
|
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
|
|
|
|
|
|
|
if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
|
|
|
|
rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
|
|
|
|
rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
|
|
|
|
tasklet_schedule(&rt2x00dev->txstatus_tasklet);
|
|
|
|
/*
|
|
|
|
* Mask out all txdone interrupts.
|
|
|
|
*/
|
|
|
|
rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
|
|
|
|
rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
|
|
|
|
rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
|
|
|
|
}
|
2010-07-11 10:26:48 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
/*
|
|
|
|
* Disable all interrupts for which a tasklet was scheduled right now,
|
|
|
|
* the tasklet will reenable the appropriate interrupts.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
2010-07-11 10:26:48 +00:00
|
|
|
|
2011-01-30 12:20:05 +00:00
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR8, ®);
|
|
|
|
reg |= mask;
|
|
|
|
rt2x00pci_register_write(rt2x00dev, CSR8, reg);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
2010-07-11 10:26:48 +00:00
|
|
|
}
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* Device probe functions.
|
|
|
|
*/
|
|
|
|
static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
struct eeprom_93cx6 eeprom;
|
|
|
|
u32 reg;
|
|
|
|
u16 word;
|
|
|
|
u8 *mac;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR21, ®);
|
|
|
|
|
|
|
|
eeprom.data = rt2x00dev;
|
|
|
|
eeprom.register_read = rt2400pci_eepromregister_read;
|
|
|
|
eeprom.register_write = rt2400pci_eepromregister_write;
|
|
|
|
eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
|
|
|
|
PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
|
|
|
|
eeprom.reg_data_in = 0;
|
|
|
|
eeprom.reg_data_out = 0;
|
|
|
|
eeprom.reg_data_clock = 0;
|
|
|
|
eeprom.reg_chip_select = 0;
|
|
|
|
|
|
|
|
eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
|
|
|
|
EEPROM_SIZE / sizeof(u16));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start validation of the data that has been read.
|
|
|
|
*/
|
|
|
|
mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
|
|
|
|
if (!is_valid_ether_addr(mac)) {
|
|
|
|
random_ether_addr(mac);
|
2008-10-27 22:59:26 +00:00
|
|
|
EEPROM(rt2x00dev, "MAC: %pM\n", mac);
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
|
|
|
|
if (word == 0xffff) {
|
|
|
|
ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
u16 value;
|
|
|
|
u16 eeprom;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read EEPROM word for configuration.
|
|
|
|
*/
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Identify RF chipset.
|
|
|
|
*/
|
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
|
2010-02-13 19:55:49 +00:00
|
|
|
rt2x00_set_chip(rt2x00dev, RT2460, value,
|
|
|
|
rt2x00_get_field32(reg, CSR0_REVISION));
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2009-12-22 23:03:25 +00:00
|
|
|
if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
|
2007-09-26 00:57:13 +00:00
|
|
|
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Identify default antenna configuration.
|
|
|
|
*/
|
2007-10-13 14:26:23 +00:00
|
|
|
rt2x00dev->default_ant.tx =
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
|
2007-10-13 14:26:23 +00:00
|
|
|
rt2x00dev->default_ant.rx =
|
2007-09-26 00:57:13 +00:00
|
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
|
|
|
|
|
2007-10-13 14:26:23 +00:00
|
|
|
/*
|
|
|
|
* When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
|
|
|
|
* I am not 100% sure about this, but the legacy drivers do not
|
|
|
|
* indicate antenna swapping in software is required when
|
|
|
|
* diversity is enabled.
|
|
|
|
*/
|
|
|
|
if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
|
|
|
|
rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
|
|
|
|
if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
|
|
|
|
rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
/*
|
|
|
|
* Store led mode, for correct led behaviour.
|
|
|
|
*/
|
2008-09-08 17:07:15 +00:00
|
|
|
#ifdef CONFIG_RT2X00_LIB_LEDS
|
2008-02-03 14:53:40 +00:00
|
|
|
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
|
|
|
|
|
2008-06-03 18:30:01 +00:00
|
|
|
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
|
2009-01-17 19:44:08 +00:00
|
|
|
if (value == LED_MODE_TXRX_ACTIVITY ||
|
|
|
|
value == LED_MODE_DEFAULT ||
|
|
|
|
value == LED_MODE_ASUS)
|
2008-06-03 18:30:01 +00:00
|
|
|
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
|
|
|
|
LED_TYPE_ACTIVITY);
|
2008-09-08 17:07:15 +00:00
|
|
|
#endif /* CONFIG_RT2X00_LIB_LEDS */
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Detect if this device has an hardware controlled radio.
|
|
|
|
*/
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
|
2007-09-25 18:55:39 +00:00
|
|
|
__set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if the BBP tuning should be enabled.
|
|
|
|
*/
|
2010-07-11 10:24:22 +00:00
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
|
|
|
|
__set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RF value list for RF2420 & RF2421
|
|
|
|
* Supports: 2.4 GHz
|
|
|
|
*/
|
2008-08-04 14:38:47 +00:00
|
|
|
static const struct rf_channel rf_vals_b[] = {
|
2007-09-26 00:57:13 +00:00
|
|
|
{ 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
|
|
|
|
{ 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
|
|
|
|
{ 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
|
|
|
|
{ 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
|
|
|
|
{ 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
|
|
|
|
{ 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
|
|
|
|
{ 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
|
|
|
|
{ 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
|
|
|
|
{ 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
|
|
|
|
{ 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
|
|
|
|
{ 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
|
|
|
|
{ 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
|
|
|
|
{ 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
|
|
|
|
{ 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
|
|
|
|
};
|
|
|
|
|
2008-08-04 14:38:47 +00:00
|
|
|
static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
2007-09-26 00:57:13 +00:00
|
|
|
{
|
|
|
|
struct hw_mode_spec *spec = &rt2x00dev->spec;
|
2008-08-04 14:38:47 +00:00
|
|
|
struct channel_info *info;
|
|
|
|
char *tx_power;
|
2007-09-26 00:57:13 +00:00
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize all hw fields.
|
|
|
|
*/
|
2008-05-08 17:15:40 +00:00
|
|
|
rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
|
2009-01-07 17:28:20 +00:00
|
|
|
IEEE80211_HW_SIGNAL_DBM |
|
|
|
|
IEEE80211_HW_SUPPORTS_PS |
|
|
|
|
IEEE80211_HW_PS_NULLFUNC_STACK;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-06-16 17:55:43 +00:00
|
|
|
SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
|
2007-09-26 00:57:13 +00:00
|
|
|
SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
|
|
|
|
rt2x00_eeprom_addr(rt2x00dev,
|
|
|
|
EEPROM_MAC_ADDR_0));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize hw_mode information.
|
|
|
|
*/
|
2008-02-17 16:35:05 +00:00
|
|
|
spec->supported_bands = SUPPORT_BAND_2GHZ;
|
|
|
|
spec->supported_rates = SUPPORT_RATE_CCK;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
2008-08-04 14:38:47 +00:00
|
|
|
spec->num_channels = ARRAY_SIZE(rf_vals_b);
|
|
|
|
spec->channels = rf_vals_b;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create channel information array
|
|
|
|
*/
|
2010-08-11 07:02:48 +00:00
|
|
|
info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
|
2008-08-04 14:38:47 +00:00
|
|
|
if (!info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
spec->channels_info = info;
|
|
|
|
|
|
|
|
tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
|
2010-08-23 17:56:07 +00:00
|
|
|
for (i = 0; i < 14; i++) {
|
|
|
|
info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
|
|
|
|
info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
|
|
|
|
}
|
2008-08-04 14:38:47 +00:00
|
|
|
|
|
|
|
return 0;
|
2007-09-26 00:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
|
|
|
|
{
|
|
|
|
int retval;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate eeprom data.
|
|
|
|
*/
|
|
|
|
retval = rt2400pci_validate_eeprom(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
retval = rt2400pci_init_eeprom(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize hw specifications.
|
|
|
|
*/
|
2008-08-04 14:38:47 +00:00
|
|
|
retval = rt2400pci_probe_hw_mode(rt2x00dev);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
2008-06-16 17:56:31 +00:00
|
|
|
* This device requires the atim queue and DMA-mapped skbs.
|
2007-09-26 00:57:13 +00:00
|
|
|
*/
|
2008-02-05 21:42:23 +00:00
|
|
|
__set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
|
2008-06-16 17:56:31 +00:00
|
|
|
__set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
|
2011-03-03 18:42:01 +00:00
|
|
|
__set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the rssi offset.
|
|
|
|
*/
|
|
|
|
rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IEEE80211 stack callback functions.
|
|
|
|
*/
|
2008-04-30 16:51:21 +00:00
|
|
|
static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
|
2007-09-26 00:57:13 +00:00
|
|
|
const struct ieee80211_tx_queue_params *params)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't support variating cw_min and cw_max variables
|
|
|
|
* per queue. So by default we only configure the TX queue,
|
|
|
|
* and ignore all other configurations.
|
|
|
|
*/
|
2008-04-30 16:51:21 +00:00
|
|
|
if (queue != 0)
|
2007-09-26 00:57:13 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (rt2x00mac_conf_tx(hw, queue, params))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write configuration to register.
|
|
|
|
*/
|
2008-02-05 21:42:23 +00:00
|
|
|
rt2400pci_config_cw(rt2x00dev,
|
|
|
|
rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
|
2007-09-26 00:57:13 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
u64 tsf;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR17, ®);
|
|
|
|
tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR16, ®);
|
|
|
|
tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
|
|
|
|
|
|
|
|
return tsf;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
|
|
|
|
{
|
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
rt2x00pci_register_read(rt2x00dev, CSR15, ®);
|
|
|
|
return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct ieee80211_ops rt2400pci_mac80211_ops = {
|
|
|
|
.tx = rt2x00mac_tx,
|
[PATCH] mac80211: revamp interface and filter configuration
Drivers are currently supposed to keep track of monitor
interfaces if they allow so-called "hard" monitor, and
they are also supposed to keep track of multicast etc.
This patch changes that, replaces the set_multicast_list()
callback with a new configure_filter() callback that takes
filter flags (FIF_*) instead of interface flags (IFF_*).
For a driver, this means it should open the filter as much
as necessary to get all frames requested by the filter flags.
Accordingly, the filter flags are named "positively", e.g.
FIF_ALLMULTI.
Multicast filtering is a bit special in that drivers that
have no multicast address filters need to allow multicast
frames through when either the FIF_ALLMULTI flag is set or
when the mc_count value is positive.
At the same time, drivers are no longer notified about
monitor interfaces at all, this means they now need to
implement the start() and stop() callbacks and the new
change_filter_flags() callback. Also, the start()/stop()
ordering changed, start() is now called *before* any
add_interface() as it really should be, and stop() after
any remove_interface().
The patch also changes the behaviour of setting the bssid
to multicast for scanning when IEEE80211_HW_NO_PROBE_FILTERING
is set; the IEEE80211_HW_NO_PROBE_FILTERING flag is removed
and the filter flag FIF_BCN_PRBRESP_PROMISC introduced.
This is a lot more efficient for hardware like b43 that
supports it and other hardware can still set the BSSID
to all-ones.
Driver modifications by Johannes Berg (b43 & iwlwifi), Michael Wu
(rtl8187, adm8211, and p54), Larry Finger (b43legacy), and
Ivo van Doorn (rt2x00).
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Signed-off-by: Michael Wu <flamingice@sourmilk.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2007-09-17 05:29:23 +00:00
|
|
|
.start = rt2x00mac_start,
|
|
|
|
.stop = rt2x00mac_stop,
|
2007-09-26 00:57:13 +00:00
|
|
|
.add_interface = rt2x00mac_add_interface,
|
|
|
|
.remove_interface = rt2x00mac_remove_interface,
|
|
|
|
.config = rt2x00mac_config,
|
2008-03-25 13:13:18 +00:00
|
|
|
.configure_filter = rt2x00mac_configure_filter,
|
2010-07-11 10:24:47 +00:00
|
|
|
.sw_scan_start = rt2x00mac_sw_scan_start,
|
|
|
|
.sw_scan_complete = rt2x00mac_sw_scan_complete,
|
2007-09-26 00:57:13 +00:00
|
|
|
.get_stats = rt2x00mac_get_stats,
|
2007-12-28 13:32:58 +00:00
|
|
|
.bss_info_changed = rt2x00mac_bss_info_changed,
|
2007-09-26 00:57:13 +00:00
|
|
|
.conf_tx = rt2400pci_conf_tx,
|
|
|
|
.get_tsf = rt2400pci_get_tsf,
|
|
|
|
.tx_last_beacon = rt2400pci_tx_last_beacon,
|
2009-07-01 13:17:35 +00:00
|
|
|
.rfkill_poll = rt2x00mac_rfkill_poll,
|
2010-11-04 19:40:11 +00:00
|
|
|
.flush = rt2x00mac_flush,
|
2007-09-26 00:57:13 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
|
|
|
|
.irq_handler = rt2400pci_interrupt,
|
2011-01-30 12:20:05 +00:00
|
|
|
.txstatus_tasklet = rt2400pci_txstatus_tasklet,
|
|
|
|
.tbtt_tasklet = rt2400pci_tbtt_tasklet,
|
|
|
|
.rxdone_tasklet = rt2400pci_rxdone_tasklet,
|
2007-09-26 00:57:13 +00:00
|
|
|
.probe_hw = rt2400pci_probe_hw,
|
|
|
|
.initialize = rt2x00pci_initialize,
|
|
|
|
.uninitialize = rt2x00pci_uninitialize,
|
2008-11-08 14:25:33 +00:00
|
|
|
.get_entry_state = rt2400pci_get_entry_state,
|
|
|
|
.clear_entry = rt2400pci_clear_entry,
|
2007-09-26 00:57:13 +00:00
|
|
|
.set_device_state = rt2400pci_set_device_state,
|
|
|
|
.rfkill_poll = rt2400pci_rfkill_poll,
|
|
|
|
.link_stats = rt2400pci_link_stats,
|
|
|
|
.reset_tuner = rt2400pci_reset_tuner,
|
|
|
|
.link_tuner = rt2400pci_link_tuner,
|
2010-12-13 11:34:54 +00:00
|
|
|
.start_queue = rt2400pci_start_queue,
|
|
|
|
.kick_queue = rt2400pci_kick_queue,
|
|
|
|
.stop_queue = rt2400pci_stop_queue,
|
2007-09-26 00:57:13 +00:00
|
|
|
.write_tx_desc = rt2400pci_write_tx_desc,
|
2008-07-09 13:12:44 +00:00
|
|
|
.write_beacon = rt2400pci_write_beacon,
|
2007-09-26 00:57:13 +00:00
|
|
|
.fill_rxdone = rt2400pci_fill_rxdone,
|
2008-03-25 13:13:18 +00:00
|
|
|
.config_filter = rt2400pci_config_filter,
|
rt2x00: Add per-interface structure
Rework the interface handling. Delete the interface structure
and replace it with a per-interface structure. This changes the
way rt2x00 handles the active interface drastically.
Copy ieee80211_bss_conf to the this rt2x00_intf structure during
the bss_info_changed() callback function. This will allow us to
reference it later, and removes the requirement for the device flag
SHORT_PREAMBLE flag which is interface specific.
Drivers receive the option to give the maximum number of virtual
interfaces the device can handle. Virtual interface support:
rt2400pci: 1 sta or 1 ap, * monitor interfaces
rt2500pci: 1 sta or 1 ap, * monitor interfaces
rt2500usb: 1 sta or 1 ap, * monitor interfaces
rt61pci: 1 sta or 4 ap, * monitor interfaces
rt73usb: 1 sta or 4 ap, * monitor interfaces
At the moment none of the drivers support AP and STA interfaces
simultaneously, this is a hardware limitation so future support
will be very unlikely.
Each interface structure receives its dedicated beacon entry,
with this we can easily work with beaconing while multiple master
mode interfaces are currently active.
The configuration handlers for the MAC, BSSID and type are
often called together since they all belong to the interface
configuration. Merge the 3 configuration calls and cleanup
the API between rt2x00lib and the drivers. While we are cleaning
up the interface configuration anyway, we might as well clean up
the configuration handler as well.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2008-02-03 14:49:59 +00:00
|
|
|
.config_intf = rt2400pci_config_intf,
|
2008-03-09 21:46:18 +00:00
|
|
|
.config_erp = rt2400pci_config_erp,
|
2008-10-29 16:17:57 +00:00
|
|
|
.config_ant = rt2400pci_config_ant,
|
2007-09-26 00:57:13 +00:00
|
|
|
.config = rt2400pci_config,
|
|
|
|
};
|
|
|
|
|
2008-02-05 21:42:23 +00:00
|
|
|
static const struct data_queue_desc rt2400pci_queue_rx = {
|
2010-11-04 19:37:22 +00:00
|
|
|
.entry_num = 24,
|
2008-02-05 21:42:23 +00:00
|
|
|
.data_size = DATA_FRAME_SIZE,
|
|
|
|
.desc_size = RXD_DESC_SIZE,
|
2008-05-10 11:46:03 +00:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 21:42:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct data_queue_desc rt2400pci_queue_tx = {
|
2010-11-04 19:37:22 +00:00
|
|
|
.entry_num = 24,
|
2008-02-05 21:42:23 +00:00
|
|
|
.data_size = DATA_FRAME_SIZE,
|
|
|
|
.desc_size = TXD_DESC_SIZE,
|
2008-05-10 11:46:03 +00:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 21:42:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct data_queue_desc rt2400pci_queue_bcn = {
|
2010-11-04 19:37:22 +00:00
|
|
|
.entry_num = 1,
|
2008-02-05 21:42:23 +00:00
|
|
|
.data_size = MGMT_FRAME_SIZE,
|
|
|
|
.desc_size = TXD_DESC_SIZE,
|
2008-05-10 11:46:03 +00:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 21:42:23 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct data_queue_desc rt2400pci_queue_atim = {
|
2010-11-04 19:37:22 +00:00
|
|
|
.entry_num = 8,
|
2008-02-05 21:42:23 +00:00
|
|
|
.data_size = DATA_FRAME_SIZE,
|
|
|
|
.desc_size = TXD_DESC_SIZE,
|
2008-05-10 11:46:03 +00:00
|
|
|
.priv_size = sizeof(struct queue_entry_priv_pci),
|
2008-02-05 21:42:23 +00:00
|
|
|
};
|
|
|
|
|
2007-09-26 00:57:13 +00:00
|
|
|
static const struct rt2x00_ops rt2400pci_ops = {
|
2009-11-23 21:44:51 +00:00
|
|
|
.name = KBUILD_MODNAME,
|
|
|
|
.max_sta_intf = 1,
|
|
|
|
.max_ap_intf = 1,
|
|
|
|
.eeprom_size = EEPROM_SIZE,
|
|
|
|
.rf_size = RF_SIZE,
|
|
|
|
.tx_queues = NUM_TX_QUEUES,
|
2009-11-23 21:44:52 +00:00
|
|
|
.extra_tx_headroom = 0,
|
2009-11-23 21:44:51 +00:00
|
|
|
.rx = &rt2400pci_queue_rx,
|
|
|
|
.tx = &rt2400pci_queue_tx,
|
|
|
|
.bcn = &rt2400pci_queue_bcn,
|
|
|
|
.atim = &rt2400pci_queue_atim,
|
|
|
|
.lib = &rt2400pci_rt2x00_ops,
|
|
|
|
.hw = &rt2400pci_mac80211_ops,
|
2007-09-26 00:57:13 +00:00
|
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
2009-11-23 21:44:51 +00:00
|
|
|
.debugfs = &rt2400pci_rt2x00debug,
|
2007-09-26 00:57:13 +00:00
|
|
|
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RT2400pci module information.
|
|
|
|
*/
|
2010-01-07 11:58:11 +00:00
|
|
|
static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
|
2007-09-26 00:57:13 +00:00
|
|
|
{ PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
|
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_AUTHOR(DRV_PROJECT);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
|
|
|
|
MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
|
|
|
|
MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
|
|
|
static struct pci_driver rt2400pci_driver = {
|
2007-11-27 20:47:34 +00:00
|
|
|
.name = KBUILD_MODNAME,
|
2007-09-26 00:57:13 +00:00
|
|
|
.id_table = rt2400pci_device_table,
|
|
|
|
.probe = rt2x00pci_probe,
|
|
|
|
.remove = __devexit_p(rt2x00pci_remove),
|
|
|
|
.suspend = rt2x00pci_suspend,
|
|
|
|
.resume = rt2x00pci_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init rt2400pci_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&rt2400pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit rt2400pci_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&rt2400pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(rt2400pci_init);
|
|
|
|
module_exit(rt2400pci_exit);
|