2009-03-10 17:53:29 +00:00
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#ifndef _ASM_POWERPC_PTE_40x_H
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#define _ASM_POWERPC_PTE_40x_H
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#ifdef __KERNEL__
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/*
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* At present, all PowerPC 400-class processors share a similar TLB
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* architecture. The instruction and data sides share a unified,
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* 64-entry, fully-associative TLB which is maintained totally under
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* software control. In addition, the instruction side has a
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* hardware-managed, 4-entry, fully-associative TLB which serves as a
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* first level to the shared TLB. These two TLBs are known as the UTLB
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* and ITLB, respectively (see "mmu.h" for definitions).
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*
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* There are several potential gotchas here. The 40x hardware TLBLO
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* field looks like this:
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*
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* 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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* RPN..................... 0 0 EX WR ZSEL....... W I M G
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*
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* Where possible we make the Linux PTE bits match up with this
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*
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* - bits 20 and 21 must be cleared, because we use 4k pages (40x can
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* support down to 1k pages), this is done in the TLBMiss exception
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* handler.
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* - We use only zones 0 (for kernel pages) and 1 (for user pages)
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* of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
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* miss handler. Bit 27 is PAGE_USER, thus selecting the correct
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* zone.
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* - PRESENT *must* be in the bottom two bits because swap cache
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* entries use the top 30 bits. Because 40x doesn't support SMP
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* anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
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* is cleared in the TLB miss handler before the TLB entry is loaded.
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* - All other bits of the PTE are loaded into TLBLO without
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* modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
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* software PTE bits. We actually use use bits 21, 24, 25, and
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* 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
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* PRESENT.
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*/
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#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
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#define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
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#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
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#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
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#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
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#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
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#define _PAGE_RW 0x040 /* software: Writes permitted */
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#define _PAGE_DIRTY 0x080 /* software: dirty page */
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#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
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2009-08-18 19:00:34 +00:00
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#define _PAGE_EXEC 0x200 /* hardware: EX permission */
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2009-03-10 17:53:29 +00:00
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#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
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#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
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#define _PMD_BAD 0x802
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#define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
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#define _PMD_SIZE_4M 0x0c0
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#define _PMD_SIZE_16M 0x0e0
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#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
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/* Until my rework is finished, 40x still needs atomic PTE updates */
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#define PTE_ATOMIC_UPDATES 1
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_40x_H */
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