2005-10-10 12:50:37 +00:00
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/*
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*
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* Common boot and setup code.
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*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/delay.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/ioport.h>
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#include <linux/console.h>
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#include <linux/utsname.h>
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#include <linux/tty.h>
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#include <linux/root_dev.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/unistd.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 02:16:44 +00:00
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#include <linux/bootmem.h>
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2006-11-11 06:25:02 +00:00
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#include <linux/pci.h>
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2005-10-10 12:50:37 +00:00
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#include <asm/io.h>
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2005-12-04 07:39:37 +00:00
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#include <asm/kdump.h>
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2005-10-10 12:50:37 +00:00
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#include <asm/prom.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/elf.h>
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#include <asm/machdep.h>
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#include <asm/paca.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/btext.h>
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#include <asm/nvram.h>
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#include <asm/setup.h>
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#include <asm/system.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/serial.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/lmb.h>
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#include <asm/firmware.h>
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2005-10-28 12:53:37 +00:00
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#include <asm/xmon.h>
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2005-11-06 22:49:43 +00:00
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#include <asm/udbg.h>
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2005-11-11 13:06:06 +00:00
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#include <asm/kexec.h>
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2005-10-10 12:50:37 +00:00
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2005-11-09 00:01:06 +00:00
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#include "setup.h"
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2005-10-10 12:50:37 +00:00
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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int have_of = 1;
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int boot_cpuid = 0;
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u64 ppc64_pft_size;
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2005-12-09 01:40:17 +00:00
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/* Pick defaults since we might want to patch instructions
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* before we've read this from the device tree.
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*/
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struct ppc64_caches ppc64_caches = {
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2006-09-06 19:34:41 +00:00
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.dline_size = 0x40,
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.log_dline_size = 6,
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.iline_size = 0x40,
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.log_iline_size = 6
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2005-12-09 01:40:17 +00:00
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};
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2005-10-10 12:50:37 +00:00
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EXPORT_SYMBOL_GPL(ppc64_caches);
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/*
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* These are used in binfmt_elf.c to put aux entries on the stack
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* for each elf executable being started.
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*/
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int dcache_bsize;
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int icache_bsize;
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int ucache_bsize;
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#ifdef CONFIG_SMP
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static int smt_enabled_cmdline;
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/* Look for ibm,smt-enabled OF option */
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static void check_smt_enabled(void)
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{
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struct device_node *dn;
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2006-07-12 05:35:54 +00:00
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const char *smt_option;
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2005-10-10 12:50:37 +00:00
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/* Allow the command line to overrule the OF option */
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if (smt_enabled_cmdline)
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return;
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dn = of_find_node_by_path("/options");
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if (dn) {
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2007-04-03 12:26:41 +00:00
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smt_option = of_get_property(dn, "ibm,smt-enabled", NULL);
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2005-10-10 12:50:37 +00:00
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if (smt_option) {
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if (!strcmp(smt_option, "on"))
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smt_enabled_at_boot = 1;
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else if (!strcmp(smt_option, "off"))
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smt_enabled_at_boot = 0;
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}
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}
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}
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/* Look for smt-enabled= cmdline option */
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static int __init early_smt_enabled(char *p)
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{
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smt_enabled_cmdline = 1;
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if (!p)
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return 0;
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if (!strcmp(p, "on") || !strcmp(p, "1"))
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smt_enabled_at_boot = 1;
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else if (!strcmp(p, "off") || !strcmp(p, "0"))
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smt_enabled_at_boot = 0;
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return 0;
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}
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early_param("smt-enabled", early_smt_enabled);
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2005-11-04 23:33:55 +00:00
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#else
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#define check_smt_enabled()
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2005-10-10 12:50:37 +00:00
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#endif /* CONFIG_SMP */
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2006-06-23 08:20:09 +00:00
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/* Put the paca pointer into r13 and SPRG3 */
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void __init setup_paca(int cpu)
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{
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local_paca = &paca[cpu];
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mtspr(SPRN_SPRG3, local_paca);
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}
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2005-10-10 12:50:37 +00:00
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/*
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* Early initialization entry point. This is called by head.S
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* with MMU translation disabled. We rely on the "feature" of
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* the CPU that ignores the top 2 bits of the address in real
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* mode so we can access kernel globals normally provided we
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* only toy with things in the RMO region. From here, we do
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* some early parsing of the device-tree to setup out LMB
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* data structures, and allocate & initialize the hash table
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* and segment tables so we can start running with translation
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* enabled.
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*
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* It is this function which will call the probe() callback of
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* the various platform types and copy the matching one to the
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* global ppc_md structure. Your platform can eventually do
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* some very early initializations from the probe() routine, but
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* this is not recommended, be very careful as, for example, the
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* device-tree is not accessible via normal means at this point.
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*/
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void __init early_setup(unsigned long dt_ptr)
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{
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2006-10-24 06:42:40 +00:00
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/* Identify CPU type */
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2006-11-10 09:38:53 +00:00
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identify_cpu(0, mfspr(SPRN_PVR));
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2006-10-24 06:42:40 +00:00
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2006-06-28 03:18:53 +00:00
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/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
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setup_paca(0);
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2006-01-11 00:54:09 +00:00
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/* Enable early debugging if any specified (see udbg.h) */
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udbg_early_init();
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2005-10-10 12:50:37 +00:00
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2006-03-28 12:15:54 +00:00
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DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
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2005-10-10 12:50:37 +00:00
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/*
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* Do early initializations using the flattened device
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* tree, like retreiving the physical memory map or
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* calculating/retreiving the hash table size
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*/
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early_init_devtree(__va(dt_ptr));
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2006-03-25 06:25:17 +00:00
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/* Now we know the logical id of our boot cpu, setup the paca. */
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2006-06-23 08:20:09 +00:00
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setup_paca(boot_cpuid);
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2006-03-25 06:25:17 +00:00
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/* Fix up paca fields required for the boot cpu */
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get_paca()->cpu_start = 1;
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get_paca()->stab_real = __pa((u64)&initial_stab);
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get_paca()->stab_addr = (u64)&initial_stab;
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2006-03-28 12:15:54 +00:00
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/* Probe the machine type */
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probe_machine();
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2005-10-10 12:50:37 +00:00
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2006-05-17 08:00:49 +00:00
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setup_kdump_trampoline();
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2005-12-04 07:39:37 +00:00
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2005-10-10 12:50:37 +00:00
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DBG("Found, Initializing memory management...\n");
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/*
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2005-11-07 00:06:55 +00:00
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* Initialize the MMU Hash table and create the linear mapping
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* of memory. Has to be done before stab/slb initialization as
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* this is currently where the page size encoding is obtained
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2005-10-10 12:50:37 +00:00
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*/
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2005-11-07 00:06:55 +00:00
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htab_initialize();
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2005-10-10 12:50:37 +00:00
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/*
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2005-11-07 00:06:55 +00:00
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* Initialize stab / SLB management except on iSeries
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2005-10-10 12:50:37 +00:00
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*/
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2006-04-01 16:45:04 +00:00
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if (cpu_has_feature(CPU_FTR_SLB))
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slb_initialize();
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else if (!firmware_has_feature(FW_FEATURE_ISERIES))
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stab_initialize(get_paca()->stab_real);
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2005-10-10 12:50:37 +00:00
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DBG(" <- early_setup()\n");
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}
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2005-11-10 02:37:51 +00:00
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#ifdef CONFIG_SMP
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void early_setup_secondary(void)
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{
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struct paca_struct *lpaca = get_paca();
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[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 06:47:49 +00:00
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/* Mark interrupts enabled in PACA */
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lpaca->soft_enabled = 0;
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2005-11-10 02:37:51 +00:00
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/* Initialize hash table for that CPU */
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htab_initialize_secondary();
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/* Initialize STAB/SLB. We use a virtual address as it works
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* in real mode on pSeries and we want a virutal address on
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* iSeries anyway
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*/
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if (cpu_has_feature(CPU_FTR_SLB))
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slb_initialize();
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else
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stab_initialize(lpaca->stab_addr);
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}
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#endif /* CONFIG_SMP */
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2005-10-10 12:50:37 +00:00
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2005-11-04 01:09:42 +00:00
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
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void smp_release_cpus(void)
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{
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extern unsigned long __secondary_hold_spinloop;
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2005-12-05 21:49:00 +00:00
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unsigned long *ptr;
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2005-11-04 01:09:42 +00:00
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DBG(" -> smp_release_cpus()\n");
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/* All secondary cpus are spinning on a common spinloop, release them
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* all now so they can start to spin on their individual paca
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* spinloops. For non SMP kernels, the secondary cpus never get out
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* of the common spinloop.
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* This is useless but harmless on iSeries, secondaries are already
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* waiting on their paca spinloops. */
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2005-12-05 21:49:00 +00:00
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ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
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- PHYSICAL_START);
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*ptr = 1;
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2005-11-04 01:09:42 +00:00
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mb();
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DBG(" <- smp_release_cpus()\n");
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}
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#endif /* CONFIG_SMP || CONFIG_KEXEC */
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2005-10-10 12:50:37 +00:00
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/*
|
2005-11-10 02:37:51 +00:00
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* Initialize some remaining members of the ppc64_caches and systemcfg
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* structures
|
2005-10-10 12:50:37 +00:00
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* (at least until we get rid of them completely). This is mostly some
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* cache informations about the CPU that will be used by cache flush
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* routines and/or provided to userland
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*/
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static void __init initialize_cache_info(void)
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{
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struct device_node *np;
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unsigned long num_cpus = 0;
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DBG(" -> initialize_cache_info()\n");
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for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) {
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num_cpus += 1;
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|
/* We're assuming *all* of the CPUs have the same
|
|
|
|
* d-cache and i-cache sizes... -Peter
|
|
|
|
*/
|
|
|
|
|
|
|
|
if ( num_cpus == 1 ) {
|
2006-07-12 05:35:54 +00:00
|
|
|
const u32 *sizep, *lsizep;
|
2005-10-10 12:50:37 +00:00
|
|
|
u32 size, lsize;
|
|
|
|
const char *dc, *ic;
|
|
|
|
|
|
|
|
/* Then read cache informations */
|
2006-03-28 12:15:54 +00:00
|
|
|
if (machine_is(powermac)) {
|
2005-10-10 12:50:37 +00:00
|
|
|
dc = "d-cache-block-size";
|
|
|
|
ic = "i-cache-block-size";
|
|
|
|
} else {
|
|
|
|
dc = "d-cache-line-size";
|
|
|
|
ic = "i-cache-line-size";
|
|
|
|
}
|
|
|
|
|
|
|
|
size = 0;
|
|
|
|
lsize = cur_cpu_spec->dcache_bsize;
|
2007-04-03 12:26:41 +00:00
|
|
|
sizep = of_get_property(np, "d-cache-size", NULL);
|
2005-10-10 12:50:37 +00:00
|
|
|
if (sizep != NULL)
|
|
|
|
size = *sizep;
|
2007-04-03 12:26:41 +00:00
|
|
|
lsizep = of_get_property(np, dc, NULL);
|
2005-10-10 12:50:37 +00:00
|
|
|
if (lsizep != NULL)
|
|
|
|
lsize = *lsizep;
|
|
|
|
if (sizep == 0 || lsizep == 0)
|
|
|
|
DBG("Argh, can't find dcache properties ! "
|
|
|
|
"sizep: %p, lsizep: %p\n", sizep, lsizep);
|
|
|
|
|
2005-11-11 10:15:21 +00:00
|
|
|
ppc64_caches.dsize = size;
|
|
|
|
ppc64_caches.dline_size = lsize;
|
2005-10-10 12:50:37 +00:00
|
|
|
ppc64_caches.log_dline_size = __ilog2(lsize);
|
|
|
|
ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
|
|
|
|
|
|
|
|
size = 0;
|
|
|
|
lsize = cur_cpu_spec->icache_bsize;
|
2007-04-03 12:26:41 +00:00
|
|
|
sizep = of_get_property(np, "i-cache-size", NULL);
|
2005-10-10 12:50:37 +00:00
|
|
|
if (sizep != NULL)
|
|
|
|
size = *sizep;
|
2007-04-03 12:26:41 +00:00
|
|
|
lsizep = of_get_property(np, ic, NULL);
|
2005-10-10 12:50:37 +00:00
|
|
|
if (lsizep != NULL)
|
|
|
|
lsize = *lsizep;
|
|
|
|
if (sizep == 0 || lsizep == 0)
|
|
|
|
DBG("Argh, can't find icache properties ! "
|
|
|
|
"sizep: %p, lsizep: %p\n", sizep, lsizep);
|
|
|
|
|
2005-11-11 10:15:21 +00:00
|
|
|
ppc64_caches.isize = size;
|
|
|
|
ppc64_caches.iline_size = lsize;
|
2005-10-10 12:50:37 +00:00
|
|
|
ppc64_caches.log_iline_size = __ilog2(lsize);
|
|
|
|
ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG(" <- initialize_cache_info()\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do some initial setup of the system. The parameters are those which
|
|
|
|
* were passed in from the bootloader.
|
|
|
|
*/
|
|
|
|
void __init setup_system(void)
|
|
|
|
{
|
|
|
|
DBG(" -> setup_system()\n");
|
|
|
|
|
2006-10-24 06:42:40 +00:00
|
|
|
/* Apply the CPUs-specific and firmware specific fixups to kernel
|
|
|
|
* text (nop out sections not relevant to this CPU or this firmware)
|
|
|
|
*/
|
2006-10-20 01:47:18 +00:00
|
|
|
do_feature_fixups(cur_cpu_spec->cpu_features,
|
2006-10-24 06:42:40 +00:00
|
|
|
&__start___ftr_fixup, &__stop___ftr_fixup);
|
2006-10-20 01:47:18 +00:00
|
|
|
do_feature_fixups(powerpc_firmware_features,
|
2006-10-24 06:42:40 +00:00
|
|
|
&__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
|
|
|
|
|
2005-10-10 12:50:37 +00:00
|
|
|
/*
|
|
|
|
* Unflatten the device-tree passed by prom_init or kexec
|
|
|
|
*/
|
|
|
|
unflatten_device_tree();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fill the ppc64_caches & systemcfg structures with informations
|
2006-07-03 11:36:01 +00:00
|
|
|
* retrieved from the device-tree.
|
2005-10-10 12:50:37 +00:00
|
|
|
*/
|
|
|
|
initialize_cache_info();
|
|
|
|
|
2006-07-03 11:36:01 +00:00
|
|
|
/*
|
|
|
|
* Initialize irq remapping subsystem
|
|
|
|
*/
|
|
|
|
irq_early_init();
|
|
|
|
|
2005-10-10 12:50:37 +00:00
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
/*
|
|
|
|
* Initialize RTAS if available
|
|
|
|
*/
|
|
|
|
rtas_initialize();
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if we have an initrd provided via the device-tree
|
|
|
|
*/
|
|
|
|
check_for_initrd();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Do some platform specific early initializations, that includes
|
|
|
|
* setting up the hash table pointers. It also sets up some interrupt-mapping
|
|
|
|
* related options that will be used by finish_device_tree()
|
|
|
|
*/
|
2006-11-10 20:01:02 +00:00
|
|
|
if (ppc_md.init_early)
|
|
|
|
ppc_md.init_early();
|
2005-10-10 12:50:37 +00:00
|
|
|
|
2005-11-23 06:56:06 +00:00
|
|
|
/*
|
|
|
|
* We can discover serial ports now since the above did setup the
|
|
|
|
* hash table management for us, thus ioremap works. We do that early
|
|
|
|
* so that further code can be debugged
|
|
|
|
*/
|
|
|
|
find_legacy_serial_ports();
|
|
|
|
|
2005-10-10 12:50:37 +00:00
|
|
|
/*
|
|
|
|
* Register early console
|
|
|
|
*/
|
|
|
|
register_early_udbg_console();
|
|
|
|
|
2006-10-03 04:12:08 +00:00
|
|
|
/*
|
|
|
|
* Initialize xmon
|
|
|
|
*/
|
|
|
|
xmon_setup();
|
2006-05-17 08:00:41 +00:00
|
|
|
|
2005-11-04 23:33:55 +00:00
|
|
|
check_smt_enabled();
|
|
|
|
smp_setup_cpu_maps();
|
2005-10-10 12:50:37 +00:00
|
|
|
|
2006-02-16 03:13:50 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2005-10-10 12:50:37 +00:00
|
|
|
/* Release secondary cpus out of their spinloops at 0x60 now that
|
|
|
|
* we can map physical -> logical CPU ids
|
|
|
|
*/
|
|
|
|
smp_release_cpus();
|
2006-02-16 03:13:50 +00:00
|
|
|
#endif
|
2005-10-10 12:50:37 +00:00
|
|
|
|
2006-10-02 09:18:13 +00:00
|
|
|
printk("Starting Linux PPC64 %s\n", init_utsname()->version);
|
2005-10-10 12:50:37 +00:00
|
|
|
|
|
|
|
printk("-----------------------------------------------------\n");
|
|
|
|
printk("ppc64_pft_size = 0x%lx\n", ppc64_pft_size);
|
2005-11-11 10:15:21 +00:00
|
|
|
printk("physicalMemorySize = 0x%lx\n", lmb_phys_mem_size());
|
2005-10-10 12:50:37 +00:00
|
|
|
printk("ppc64_caches.dcache_line_size = 0x%x\n",
|
2005-11-11 10:15:21 +00:00
|
|
|
ppc64_caches.dline_size);
|
2005-10-10 12:50:37 +00:00
|
|
|
printk("ppc64_caches.icache_line_size = 0x%x\n",
|
2005-11-11 10:15:21 +00:00
|
|
|
ppc64_caches.iline_size);
|
2005-10-10 12:50:37 +00:00
|
|
|
printk("htab_address = 0x%p\n", htab_address);
|
|
|
|
printk("htab_hash_mask = 0x%lx\n", htab_hash_mask);
|
2005-12-04 07:39:23 +00:00
|
|
|
#if PHYSICAL_START > 0
|
|
|
|
printk("physical_start = 0x%x\n", PHYSICAL_START);
|
|
|
|
#endif
|
2005-10-10 12:50:37 +00:00
|
|
|
printk("-----------------------------------------------------\n");
|
|
|
|
|
|
|
|
DBG(" <- setup_system()\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_IRQSTACKS
|
|
|
|
static void __init irqstack_early_init(void)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* interrupt stacks must be under 256MB, we cannot afford to take
|
|
|
|
* SLB misses on them.
|
|
|
|
*/
|
2006-03-28 22:50:51 +00:00
|
|
|
for_each_possible_cpu(i) {
|
2005-11-07 00:06:55 +00:00
|
|
|
softirq_ctx[i] = (struct thread_info *)
|
|
|
|
__va(lmb_alloc_base(THREAD_SIZE,
|
|
|
|
THREAD_SIZE, 0x10000000));
|
|
|
|
hardirq_ctx[i] = (struct thread_info *)
|
|
|
|
__va(lmb_alloc_base(THREAD_SIZE,
|
|
|
|
THREAD_SIZE, 0x10000000));
|
2005-10-10 12:50:37 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define irqstack_early_init()
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stack space used when we detect a bad kernel stack pointer, and
|
|
|
|
* early in SMP boots before relocation is enabled.
|
|
|
|
*/
|
|
|
|
static void __init emergency_stack_init(void)
|
|
|
|
{
|
|
|
|
unsigned long limit;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Emergency stacks must be under 256MB, we cannot afford to take
|
|
|
|
* SLB misses on them. The ABI also requires them to be 128-byte
|
|
|
|
* aligned.
|
|
|
|
*
|
|
|
|
* Since we use these as temporary stacks during secondary CPU
|
|
|
|
* bringup, we need to get at them in real mode. This means they
|
|
|
|
* must also be within the RMO region.
|
|
|
|
*/
|
|
|
|
limit = min(0x10000000UL, lmb.rmo_size);
|
|
|
|
|
2006-03-28 22:50:51 +00:00
|
|
|
for_each_possible_cpu(i)
|
2005-11-07 00:06:55 +00:00
|
|
|
paca[i].emergency_sp =
|
|
|
|
__va(lmb_alloc_base(HW_PAGE_SIZE, 128, limit)) + HW_PAGE_SIZE;
|
2005-10-10 12:50:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Called into from start_kernel, after lock_kernel has been called.
|
|
|
|
* Initializes bootmem, which is unsed to manage page allocation until
|
|
|
|
* mem_init is called.
|
|
|
|
*/
|
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
|
|
{
|
|
|
|
ppc64_boot_msg(0x12, "Setup Arch");
|
|
|
|
|
|
|
|
*cmdline_p = cmd_line;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set cache line size based on type of cpu as a default.
|
|
|
|
* Systems with OF can look in the properties on the cpu node(s)
|
|
|
|
* for a possibly more accurate value.
|
|
|
|
*/
|
|
|
|
dcache_bsize = ppc64_caches.dline_size;
|
|
|
|
icache_bsize = ppc64_caches.iline_size;
|
|
|
|
|
|
|
|
/* reboot on panic */
|
|
|
|
panic_timeout = 180;
|
|
|
|
|
|
|
|
if (ppc_md.panic)
|
2006-05-05 05:02:08 +00:00
|
|
|
setup_panic();
|
2005-10-10 12:50:37 +00:00
|
|
|
|
|
|
|
init_mm.start_code = PAGE_OFFSET;
|
|
|
|
init_mm.end_code = (unsigned long) _etext;
|
|
|
|
init_mm.end_data = (unsigned long) _edata;
|
|
|
|
init_mm.brk = klimit;
|
|
|
|
|
|
|
|
irqstack_early_init();
|
|
|
|
emergency_stack_init();
|
|
|
|
|
|
|
|
stabs_alloc();
|
|
|
|
|
|
|
|
/* set up the bootmem stuff with available memory */
|
|
|
|
do_init_bootmem();
|
|
|
|
sparse_init();
|
|
|
|
|
2005-10-20 11:00:20 +00:00
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
|
|
conswitchp = &dummy_con;
|
|
|
|
#endif
|
|
|
|
|
2005-10-10 12:50:37 +00:00
|
|
|
ppc_md.setup_arch();
|
|
|
|
|
|
|
|
paging_init();
|
|
|
|
ppc64_boot_msg(0x15, "Setup Done");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* ToDo: do something useful if ppc_md is not yet setup. */
|
|
|
|
#define PPC64_LINUX_FUNCTION 0x0f000000
|
|
|
|
#define PPC64_IPL_MESSAGE 0xc0000000
|
|
|
|
#define PPC64_TERM_MESSAGE 0xb0000000
|
|
|
|
|
|
|
|
static void ppc64_do_msg(unsigned int src, const char *msg)
|
|
|
|
{
|
|
|
|
if (ppc_md.progress) {
|
|
|
|
char buf[128];
|
|
|
|
|
|
|
|
sprintf(buf, "%08X\n", src);
|
|
|
|
ppc_md.progress(buf, 0);
|
|
|
|
snprintf(buf, 128, "%s", msg);
|
|
|
|
ppc_md.progress(buf, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Print a boot progress message. */
|
|
|
|
void ppc64_boot_msg(unsigned int src, const char *msg)
|
|
|
|
{
|
|
|
|
ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg);
|
|
|
|
printk("[boot]%04x %s\n", src, msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Print a termination message (print only -- does not stop the kernel) */
|
|
|
|
void ppc64_terminate_msg(unsigned int src, const char *msg)
|
|
|
|
{
|
|
|
|
ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_TERM_MESSAGE|src, msg);
|
|
|
|
printk("[terminate]%04x %s\n", src, msg);
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_die(void)
|
|
|
|
{
|
|
|
|
if (ppc_md.cpu_die)
|
|
|
|
ppc_md.cpu_die();
|
|
|
|
}
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 02:16:44 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
void __init setup_per_cpu_areas(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
unsigned long size;
|
|
|
|
char *ptr;
|
|
|
|
|
|
|
|
/* Copy section for each CPU (we discard the original) */
|
2007-05-02 17:27:12 +00:00
|
|
|
size = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE);
|
[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 02:16:44 +00:00
|
|
|
#ifdef CONFIG_MODULES
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|
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if (size < PERCPU_ENOUGH_ROOM)
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size = PERCPU_ENOUGH_ROOM;
|
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#endif
|
|
|
|
|
2006-03-28 22:50:51 +00:00
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|
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for_each_possible_cpu(i) {
|
2007-05-02 17:27:12 +00:00
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ptr = alloc_bootmem_pages_node(NODE_DATA(cpu_to_node(i)), size);
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[PATCH] powerpc/64: per cpu data optimisations
The current ppc64 per cpu data implementation is quite slow. eg:
lhz 11,18(13) /* smp_processor_id() */
ld 9,.LC63-.LCTOC1(30) /* per_cpu__variable_name */
ld 8,.LC61-.LCTOC1(30) /* __per_cpu_offset */
sldi 11,11,3 /* form index into __per_cpu_offset */
mr 10,9
ldx 9,11,8 /* __per_cpu_offset[smp_processor_id()] */
ldx 0,10,9 /* load per cpu data */
5 loads for something that is supposed to be fast, pretty awful. One
reason for the large number of loads is that we have to synthesize 2
64bit constants (per_cpu__variable_name and __per_cpu_offset).
By putting __per_cpu_offset into the paca we can avoid the 2 loads
associated with it:
ld 11,56(13) /* paca->data_offset */
ld 9,.LC59-.LCTOC1(30) /* per_cpu__variable_name */
ldx 0,9,11 /* load per cpu data
Longer term we can should be able to do even better than 3 loads.
If per_cpu__variable_name wasnt a 64bit constant and paca->data_offset
was in a register we could cut it down to one load. A suggestion from
Rusty is to use gcc's __thread extension here. In order to do this we
would need to free up r13 (the __thread register and where the paca
currently is). So far Ive had a few unsuccessful attempts at doing that :)
The patch also allocates per cpu memory node local on NUMA machines.
This patch from Rusty has been sitting in my queue _forever_ but stalled
when I hit the compiler bug. Sorry about that.
Finally I also only allocate per cpu data for possible cpus, which comes
straight out of the x86-64 port. On a pseries kernel (with NR_CPUS == 128)
and 4 possible cpus we see some nice gains:
total used free shared buffers cached
Mem: 4012228 212860 3799368 0 0 162424
total used free shared buffers cached
Mem: 4016200 212984 3803216 0 0 162424
A saving of 3.75MB. Quite nice for smaller machines. Note: we now have
to be careful of per cpu users that touch data for !possible cpus.
At this stage it might be worth making the NUMA and possible cpu
optimisations generic, but per cpu init is done so early we have to be
careful that all architectures have their possible map setup correctly.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-01-11 02:16:44 +00:00
|
|
|
if (!ptr)
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|
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panic("Cannot allocate cpu data for CPU %d\n", i);
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paca[i].data_offset = ptr - __per_cpu_start;
|
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memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
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}
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}
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#endif
|
[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 06:25:10 +00:00
|
|
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|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_INDIRECT_IO
|
|
|
|
struct ppc_pci_io ppc_pci_io;
|
|
|
|
EXPORT_SYMBOL(ppc_pci_io);
|
|
|
|
#endif /* CONFIG_PPC_INDIRECT_IO */
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