2007-02-11 17:31:01 +00:00
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/* linux/arch/arm/plat-s3c24xx/clock.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX Core clock control support
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*
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* Based on, and code from linux/arch/arm/mach-versatile/clock.c
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**
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** Copyright (C) 2004 ARM Limited.
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** Written by Deep Blue Solutions Limited.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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2008-08-05 15:14:15 +00:00
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#include <mach/hardware.h>
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2007-02-11 17:31:01 +00:00
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#include <asm/irq.h>
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#include <asm/io.h>
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2008-08-05 15:14:15 +00:00
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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2007-02-11 17:31:01 +00:00
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/cpu.h>
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/* clock information */
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static LIST_HEAD(clocks);
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DEFINE_MUTEX(clocks_mutex);
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/* enable and disable calls for use with the clk struct */
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static int clk_null_enable(struct clk *clk, int enable)
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{
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return 0;
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}
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/* Clock API calls */
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struct clk *clk_get(struct device *dev, const char *id)
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{
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struct clk *p;
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struct clk *clk = ERR_PTR(-ENOENT);
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int idno;
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if (dev == NULL || dev->bus != &platform_bus_type)
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idno = -1;
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else
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idno = to_platform_device(dev)->id;
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mutex_lock(&clocks_mutex);
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list_for_each_entry(p, &clocks, list) {
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if (p->id == idno &&
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strcmp(id, p->name) == 0 &&
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try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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/* check for the case where a device was supplied, but the
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* clock that was being searched for is not device specific */
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if (IS_ERR(clk)) {
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list_for_each_entry(p, &clocks, list) {
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if (p->id == -1 && strcmp(id, p->name) == 0 &&
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try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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}
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mutex_unlock(&clocks_mutex);
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return clk;
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}
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void clk_put(struct clk *clk)
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{
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module_put(clk->owner);
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}
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int clk_enable(struct clk *clk)
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{
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if (IS_ERR(clk) || clk == NULL)
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return -EINVAL;
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clk_enable(clk->parent);
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mutex_lock(&clocks_mutex);
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if ((clk->usage++) == 0)
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(clk->enable)(clk, 1);
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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void clk_disable(struct clk *clk)
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{
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if (IS_ERR(clk) || clk == NULL)
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return;
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mutex_lock(&clocks_mutex);
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if ((--clk->usage) == 0)
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(clk->enable)(clk, 0);
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mutex_unlock(&clocks_mutex);
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clk_disable(clk->parent);
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}
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (IS_ERR(clk))
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return 0;
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if (clk->rate != 0)
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return clk->rate;
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if (clk->get_rate != NULL)
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return (clk->get_rate)(clk);
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if (clk->parent != NULL)
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return clk_get_rate(clk->parent);
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return clk->rate;
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}
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (!IS_ERR(clk) && clk->round_rate)
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return (clk->round_rate)(clk, rate);
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return rate;
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret;
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if (IS_ERR(clk))
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return -EINVAL;
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2008-01-28 12:01:17 +00:00
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/* We do not default just do a clk->rate = rate as
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* the clock may have been made this way by choice.
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*/
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WARN_ON(clk->set_rate == NULL);
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if (clk->set_rate == NULL)
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return -EINVAL;
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2007-02-11 17:31:01 +00:00
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mutex_lock(&clocks_mutex);
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ret = (clk->set_rate)(clk, rate);
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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struct clk *clk_get_parent(struct clk *clk)
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{
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return clk->parent;
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}
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int ret = 0;
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if (IS_ERR(clk))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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if (clk->set_parent)
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ret = (clk->set_parent)(clk, parent);
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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EXPORT_SYMBOL(clk_get);
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EXPORT_SYMBOL(clk_put);
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EXPORT_SYMBOL(clk_enable);
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EXPORT_SYMBOL(clk_disable);
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EXPORT_SYMBOL(clk_get_rate);
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EXPORT_SYMBOL(clk_round_rate);
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EXPORT_SYMBOL(clk_set_rate);
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EXPORT_SYMBOL(clk_get_parent);
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EXPORT_SYMBOL(clk_set_parent);
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/* base clocks */
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2008-01-28 12:01:17 +00:00
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static int clk_default_setrate(struct clk *clk, unsigned long rate)
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{
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clk->rate = rate;
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return 0;
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}
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2007-02-11 17:31:01 +00:00
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struct clk clk_xtal = {
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.name = "xtal",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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};
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struct clk clk_mpll = {
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.name = "mpll",
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.id = -1,
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2008-01-28 12:01:17 +00:00
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.set_rate = clk_default_setrate,
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2007-02-11 17:31:01 +00:00
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};
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struct clk clk_upll = {
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.name = "upll",
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.id = -1,
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.parent = NULL,
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.ctrlbit = 0,
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};
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struct clk clk_f = {
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.name = "fclk",
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.id = -1,
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.rate = 0,
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.parent = &clk_mpll,
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.ctrlbit = 0,
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2008-01-28 12:01:17 +00:00
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.set_rate = clk_default_setrate,
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2007-02-11 17:31:01 +00:00
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};
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struct clk clk_h = {
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.name = "hclk",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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2008-01-28 12:01:17 +00:00
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.set_rate = clk_default_setrate,
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2007-02-11 17:31:01 +00:00
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};
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struct clk clk_p = {
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.name = "pclk",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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2008-01-28 12:01:17 +00:00
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.set_rate = clk_default_setrate,
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2007-02-11 17:31:01 +00:00
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};
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struct clk clk_usb_bus = {
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.name = "usb-bus",
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.id = -1,
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.rate = 0,
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.parent = &clk_upll,
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};
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/* clocks that could be registered by external code */
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static int s3c24xx_dclk_enable(struct clk *clk, int enable)
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{
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unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
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if (enable)
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dclkcon |= clk->ctrlbit;
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else
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dclkcon &= ~clk->ctrlbit;
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__raw_writel(dclkcon, S3C24XX_DCLKCON);
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return 0;
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}
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static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long dclkcon;
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unsigned int uclk;
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if (parent == &clk_upll)
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uclk = 1;
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else if (parent == &clk_p)
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uclk = 0;
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else
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return -EINVAL;
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clk->parent = parent;
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dclkcon = __raw_readl(S3C24XX_DCLKCON);
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if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
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} else {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
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}
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__raw_writel(dclkcon, S3C24XX_DCLKCON);
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return 0;
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}
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2008-04-12 14:08:15 +00:00
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static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
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{
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unsigned long div;
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if ((rate == 0) || !clk->parent)
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return 0;
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div = clk_get_rate(clk->parent) / rate;
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if (div < 2)
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div = 2;
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else if (div > 16)
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div = 16;
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return div;
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}
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static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long div = s3c24xx_calc_div(clk, rate);
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if (div == 0)
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return 0;
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return clk_get_rate(clk->parent) / div;
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}
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static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
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if (div == 0)
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return -EINVAL;
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if (clk == &s3c24xx_dclk0) {
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mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
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S3C2410_DCLKCON_DCLK0_CMP_MASK;
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data = S3C2410_DCLKCON_DCLK0_DIV(div) |
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S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
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} else if (clk == &s3c24xx_dclk1) {
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mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
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S3C2410_DCLKCON_DCLK1_CMP_MASK;
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data = S3C2410_DCLKCON_DCLK1_DIV(div) |
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S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
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} else
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return -EINVAL;
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clk->rate = clk_get_rate(clk->parent) / div;
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__raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
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S3C24XX_DCLKCON);
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return clk->rate;
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}
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2007-02-11 17:31:01 +00:00
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static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long mask;
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unsigned long source;
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/* calculate the MISCCR setting for the clock */
|
|
|
|
|
|
|
|
if (parent == &clk_xtal)
|
|
|
|
source = S3C2410_MISCCR_CLK0_MPLL;
|
|
|
|
else if (parent == &clk_upll)
|
|
|
|
source = S3C2410_MISCCR_CLK0_UPLL;
|
|
|
|
else if (parent == &clk_f)
|
|
|
|
source = S3C2410_MISCCR_CLK0_FCLK;
|
|
|
|
else if (parent == &clk_h)
|
|
|
|
source = S3C2410_MISCCR_CLK0_HCLK;
|
|
|
|
else if (parent == &clk_p)
|
|
|
|
source = S3C2410_MISCCR_CLK0_PCLK;
|
|
|
|
else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
|
|
|
|
source = S3C2410_MISCCR_CLK0_DCLK0;
|
|
|
|
else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
|
|
|
|
source = S3C2410_MISCCR_CLK0_DCLK0;
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
clk->parent = parent;
|
|
|
|
|
2008-05-03 06:53:14 +00:00
|
|
|
if (clk == &s3c24xx_clkout0)
|
2007-02-11 17:31:01 +00:00
|
|
|
mask = S3C2410_MISCCR_CLK0_MASK;
|
|
|
|
else {
|
|
|
|
source <<= 4;
|
|
|
|
mask = S3C2410_MISCCR_CLK1_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
s3c2410_modify_misccr(mask, source);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* external clock definitions */
|
|
|
|
|
|
|
|
struct clk s3c24xx_dclk0 = {
|
|
|
|
.name = "dclk0",
|
|
|
|
.id = -1,
|
|
|
|
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
|
|
|
|
.enable = s3c24xx_dclk_enable,
|
|
|
|
.set_parent = s3c24xx_dclk_setparent,
|
2008-04-12 14:08:15 +00:00
|
|
|
.set_rate = s3c24xx_set_dclk_rate,
|
|
|
|
.round_rate = s3c24xx_round_dclk_rate,
|
2007-02-11 17:31:01 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct clk s3c24xx_dclk1 = {
|
|
|
|
.name = "dclk1",
|
|
|
|
.id = -1,
|
2008-05-03 06:53:14 +00:00
|
|
|
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
|
2007-02-11 17:31:01 +00:00
|
|
|
.enable = s3c24xx_dclk_enable,
|
|
|
|
.set_parent = s3c24xx_dclk_setparent,
|
2008-04-12 14:08:15 +00:00
|
|
|
.set_rate = s3c24xx_set_dclk_rate,
|
|
|
|
.round_rate = s3c24xx_round_dclk_rate,
|
2007-02-11 17:31:01 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct clk s3c24xx_clkout0 = {
|
|
|
|
.name = "clkout0",
|
|
|
|
.id = -1,
|
|
|
|
.set_parent = s3c24xx_clkout_setparent,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct clk s3c24xx_clkout1 = {
|
|
|
|
.name = "clkout1",
|
|
|
|
.id = -1,
|
|
|
|
.set_parent = s3c24xx_clkout_setparent,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct clk s3c24xx_uclk = {
|
|
|
|
.name = "uclk",
|
|
|
|
.id = -1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* initialise the clock system */
|
|
|
|
|
|
|
|
int s3c24xx_register_clock(struct clk *clk)
|
|
|
|
{
|
|
|
|
clk->owner = THIS_MODULE;
|
|
|
|
|
|
|
|
if (clk->enable == NULL)
|
|
|
|
clk->enable = clk_null_enable;
|
|
|
|
|
|
|
|
/* add to the list of available clocks */
|
|
|
|
|
|
|
|
mutex_lock(&clocks_mutex);
|
|
|
|
list_add(&clk->list, &clocks);
|
|
|
|
mutex_unlock(&clocks_mutex);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-04-20 10:15:27 +00:00
|
|
|
int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
|
|
|
|
{
|
|
|
|
int fails = 0;
|
|
|
|
|
|
|
|
for (; nr_clks > 0; nr_clks--, clks++) {
|
|
|
|
if (s3c24xx_register_clock(*clks) < 0)
|
|
|
|
fails++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fails;
|
|
|
|
}
|
|
|
|
|
2007-02-11 17:31:01 +00:00
|
|
|
/* initalise all the clocks */
|
|
|
|
|
|
|
|
int __init s3c24xx_setup_clocks(unsigned long xtal,
|
|
|
|
unsigned long fclk,
|
|
|
|
unsigned long hclk,
|
|
|
|
unsigned long pclk)
|
|
|
|
{
|
|
|
|
printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
|
|
|
|
|
|
|
|
/* initialise the main system clocks */
|
|
|
|
|
|
|
|
clk_xtal.rate = xtal;
|
|
|
|
clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
|
|
|
|
|
|
|
|
clk_mpll.rate = fclk;
|
|
|
|
clk_h.rate = hclk;
|
|
|
|
clk_p.rate = pclk;
|
|
|
|
clk_f.rate = fclk;
|
|
|
|
|
|
|
|
/* assume uart clocks are correctly setup */
|
|
|
|
|
|
|
|
/* register our clocks */
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_xtal) < 0)
|
|
|
|
printk(KERN_ERR "failed to register master xtal\n");
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_mpll) < 0)
|
|
|
|
printk(KERN_ERR "failed to register mpll clock\n");
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_upll) < 0)
|
|
|
|
printk(KERN_ERR "failed to register upll clock\n");
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_f) < 0)
|
|
|
|
printk(KERN_ERR "failed to register cpu fclk\n");
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_h) < 0)
|
|
|
|
printk(KERN_ERR "failed to register cpu hclk\n");
|
|
|
|
|
|
|
|
if (s3c24xx_register_clock(&clk_p) < 0)
|
|
|
|
printk(KERN_ERR "failed to register cpu pclk\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|