2010-01-06 23:07:20 +00:00
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/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2011-06-16 11:01:34 +00:00
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#include <asm/io.h>
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2010-01-06 23:07:20 +00:00
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#include "dwmac1000.h"
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_core_init(void __iomem *ioaddr)
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2010-01-06 23:07:20 +00:00
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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value |= GMAC_CORE_INIT;
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writel(value, ioaddr + GMAC_CONTROL);
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/* Mask GMAC interrupts */
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writel(0x207, ioaddr + GMAC_INT_MASK);
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#ifdef STMMAC_VLAN_TAG_USED
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/* Tag detection without filtering */
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writel(0x0, ioaddr + GMAC_VLAN_TAG);
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#endif
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}
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2010-09-17 03:23:40 +00:00
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static int dwmac1000_rx_coe_supported(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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value |= GMAC_CONTROL_IPC;
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writel(value, ioaddr + GMAC_CONTROL);
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value = readl(ioaddr + GMAC_CONTROL);
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return !!(value & GMAC_CONTROL_IPC);
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_dump_regs(void __iomem *ioaddr)
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2010-01-06 23:07:20 +00:00
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{
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int i;
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2010-08-31 04:55:17 +00:00
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pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
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2010-01-06 23:07:20 +00:00
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for (i = 0; i < 55; i++) {
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int offset = i * 4;
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pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
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offset, readl(ioaddr + offset));
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}
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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2010-01-06 23:07:20 +00:00
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unsigned int reg_n)
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{
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stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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2010-01-06 23:07:20 +00:00
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unsigned int reg_n)
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{
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stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac1000_set_filter(struct net_device *dev)
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{
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2010-08-23 20:40:42 +00:00
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void __iomem *ioaddr = (void __iomem *) dev->base_addr;
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2010-01-06 23:07:20 +00:00
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unsigned int value = 0;
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
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__func__, netdev_mc_count(dev), netdev_uc_count(dev));
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2010-01-06 23:07:20 +00:00
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if (dev->flags & IFF_PROMISC)
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value = GMAC_FRAME_FILTER_PR;
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2010-02-08 04:30:35 +00:00
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else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
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2010-01-06 23:07:20 +00:00
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|| (dev->flags & IFF_ALLMULTI)) {
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value = GMAC_FRAME_FILTER_PM; /* pass all multi */
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writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
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2010-02-08 04:30:35 +00:00
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} else if (!netdev_mc_empty(dev)) {
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2010-01-06 23:07:20 +00:00
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u32 mc_filter[2];
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2010-04-01 21:22:57 +00:00
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struct netdev_hw_addr *ha;
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2010-01-06 23:07:20 +00:00
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/* Hash filter for multicast */
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value = GMAC_FRAME_FILTER_HMC;
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memset(mc_filter, 0, sizeof(mc_filter));
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2010-04-01 21:22:57 +00:00
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netdev_for_each_mc_addr(ha, dev) {
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2010-01-06 23:07:20 +00:00
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/* The upper 6 bits of the calculated CRC are used to
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index the contens of the hash table */
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int bit_nr =
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2010-04-01 21:22:57 +00:00
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bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
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2010-01-06 23:07:20 +00:00
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register. */
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
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writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
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}
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/* Handle multiple unicast addresses (perfect filtering)*/
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2010-01-25 21:36:10 +00:00
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if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES)
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2010-01-06 23:07:20 +00:00
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/* Switch to promiscuous mode is more than 16 addrs
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are required */
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value |= GMAC_FRAME_FILTER_PR;
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else {
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int reg = 1;
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struct netdev_hw_addr *ha;
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2010-01-25 21:36:10 +00:00
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netdev_for_each_uc_addr(ha, dev) {
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dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
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reg++;
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2010-01-06 23:07:20 +00:00
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}
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}
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#ifdef FRAME_FILTER_DEBUG
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/* Enable Receive all mode (to debug filtering_fail errors) */
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value |= GMAC_FRAME_FILTER_RA;
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#endif
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writel(value, ioaddr + GMAC_FRAME_FILTER);
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
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2010-01-06 23:07:20 +00:00
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"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
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readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
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2010-01-06 23:07:20 +00:00
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unsigned int fc, unsigned int pause_time)
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{
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unsigned int flow = 0;
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
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2010-01-06 23:07:20 +00:00
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if (fc & FLOW_RX) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
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2010-01-06 23:07:20 +00:00
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flow |= GMAC_FLOW_CTRL_RFE;
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}
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if (fc & FLOW_TX) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
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2010-01-06 23:07:20 +00:00
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flow |= GMAC_FLOW_CTRL_TFE;
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}
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if (duplex) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
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2010-01-06 23:07:20 +00:00
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flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
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}
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writel(flow, ioaddr + GMAC_FLOW_CTRL);
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
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2010-01-06 23:07:20 +00:00
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{
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unsigned int pmt = 0;
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2011-04-13 18:51:43 +00:00
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if (mode & WAKE_MAGIC) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
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2010-01-06 23:07:20 +00:00
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pmt |= power_down | magic_pkt_en;
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2011-04-13 18:51:43 +00:00
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}
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if (mode & WAKE_UCAST) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
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2010-01-06 23:07:20 +00:00
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pmt |= global_unicast;
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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2010-08-23 20:40:42 +00:00
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static void dwmac1000_irq_status(void __iomem *ioaddr)
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2010-01-06 23:07:20 +00:00
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{
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u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & mmc_tx_irq))
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
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2010-01-06 23:07:20 +00:00
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readl(ioaddr + GMAC_MMC_TX_INTR));
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if (unlikely(intr_status & mmc_rx_irq))
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
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2010-01-06 23:07:20 +00:00
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readl(ioaddr + GMAC_MMC_RX_INTR));
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if (unlikely(intr_status & mmc_rx_csum_offload_irq))
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
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2010-01-06 23:07:20 +00:00
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readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
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if (unlikely(intr_status & pmt_irq)) {
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2010-04-13 20:21:12 +00:00
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CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
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2010-01-06 23:07:20 +00:00
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/* clear the PMT bits 5 and 6 by reading the PMT
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* status register. */
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readl(ioaddr + GMAC_PMT);
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}
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}
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2010-10-13 14:51:25 +00:00
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static const struct stmmac_ops dwmac1000_ops = {
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2010-01-06 23:07:20 +00:00
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.core_init = dwmac1000_core_init,
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2010-09-17 03:23:40 +00:00
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.rx_coe = dwmac1000_rx_coe_supported,
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2010-01-06 23:07:20 +00:00
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.dump_regs = dwmac1000_dump_regs,
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.host_irq_status = dwmac1000_irq_status,
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.set_filter = dwmac1000_set_filter,
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.flow_ctrl = dwmac1000_flow_ctrl,
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.pmt = dwmac1000_pmt,
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.set_umac_addr = dwmac1000_set_umac_addr,
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.get_umac_addr = dwmac1000_get_umac_addr,
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};
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2010-08-23 20:40:42 +00:00
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struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
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2010-01-06 23:07:20 +00:00
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{
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struct mac_device_info *mac;
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2011-09-01 21:51:40 +00:00
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u32 hwid = readl(ioaddr + GMAC_VERSION);
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2010-01-06 23:07:20 +00:00
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mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
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2010-07-22 01:16:48 +00:00
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if (!mac)
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return NULL;
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2010-01-06 23:07:20 +00:00
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mac->mac = &dwmac1000_ops;
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mac->dma = &dwmac1000_dma_ops;
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mac->link.port = GMAC_CONTROL_PS;
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mac->link.duplex = GMAC_CONTROL_DM;
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mac->link.speed = GMAC_CONTROL_FES;
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mac->mii.addr = GMAC_MII_ADDR;
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mac->mii.data = GMAC_MII_DATA;
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2011-09-01 21:51:40 +00:00
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mac->synopsys_uid = hwid;
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2010-01-06 23:07:20 +00:00
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return mac;
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}
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