2008-04-08 16:20:43 +00:00
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#include <linux/dma-mapping.h>
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2008-04-08 16:20:51 +00:00
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#include <linux/dmar.h>
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2008-04-08 16:20:54 +00:00
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#include <linux/bootmem.h>
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2008-04-08 16:20:51 +00:00
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2008-04-08 16:20:54 +00:00
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#include <asm/proto.h>
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#include <asm/dma.h>
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2008-04-08 16:20:51 +00:00
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#include <asm/gart.h>
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#include <asm/calgary.h>
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2008-04-08 16:20:43 +00:00
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2008-04-08 16:20:50 +00:00
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const struct dma_mapping_ops *dma_ops;
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EXPORT_SYMBOL(dma_ops);
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2008-04-08 16:20:52 +00:00
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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#else
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int panic_on_overflow __read_mostly = 0;
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int force_iommu __read_mostly = 0;
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#endif
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2008-04-08 16:20:43 +00:00
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int dma_set_mask(struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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EXPORT_SYMBOL(dma_set_mask);
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2008-04-08 16:20:54 +00:00
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#ifdef CONFIG_X86_64
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static __initdata void *dma32_bootmem_ptr;
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static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
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static int __init parse_dma32_size_opt(char *p)
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{
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if (!p)
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return -EINVAL;
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dma32_bootmem_size = memparse(p, &p);
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return 0;
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}
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early_param("dma32_size", parse_dma32_size_opt);
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void __init dma32_reserve_bootmem(void)
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{
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unsigned long size, align;
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if (end_pfn <= MAX_DMA32_PFN)
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return;
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align = 64ULL<<20;
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size = round_up(dma32_bootmem_size, align);
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dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
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__pa(MAX_DMA_ADDRESS));
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if (dma32_bootmem_ptr)
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dma32_bootmem_size = size;
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else
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dma32_bootmem_size = 0;
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}
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static void __init dma32_free_bootmem(void)
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{
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int node;
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if (end_pfn <= MAX_DMA32_PFN)
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return;
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if (!dma32_bootmem_ptr)
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return;
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for_each_online_node(node)
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free_bootmem_node(NODE_DATA(node), __pa(dma32_bootmem_ptr),
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dma32_bootmem_size);
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dma32_bootmem_ptr = NULL;
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dma32_bootmem_size = 0;
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}
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void __init pci_iommu_alloc(void)
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{
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/* free the range so iommu could get some range less than 4G */
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dma32_free_bootmem();
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/*
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* The order of these functions is important for
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* fall-back/fail-over reasons
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*/
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#ifdef CONFIG_GART_IOMMU
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gart_iommu_hole_init();
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#endif
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#ifdef CONFIG_CALGARY_IOMMU
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detect_calgary();
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#endif
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detect_intel_iommu();
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#ifdef CONFIG_SWIOTLB
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pci_swiotlb_init();
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#endif
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}
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#endif
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2008-04-08 16:20:51 +00:00
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static int __init pci_iommu_init(void)
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{
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#ifdef CONFIG_CALGARY_IOMMU
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calgary_iommu_init();
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#endif
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intel_iommu_init();
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#ifdef CONFIG_GART_IOMMU
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gart_iommu_init();
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#endif
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2008-04-08 16:20:43 +00:00
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2008-04-08 16:20:51 +00:00
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no_iommu_init();
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return 0;
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}
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void pci_iommu_shutdown(void)
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{
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gart_iommu_shutdown();
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}
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/* Must execute after PCI subsystem */
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fs_initcall(pci_iommu_init);
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