2008-08-20 03:49:59 +00:00
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#include <linux/interrupt.h>
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2008-07-10 18:16:40 +00:00
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#include <linux/dmar.h>
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2008-07-10 18:16:43 +00:00
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/pci.h>
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2008-07-10 18:16:44 +00:00
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#include <linux/irq.h>
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2008-07-10 18:16:40 +00:00
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#include <asm/io_apic.h>
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#include "intel-iommu.h"
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#include "intr_remapping.h"
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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2008-07-10 18:16:43 +00:00
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int intr_remapping_enabled;
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2008-08-20 03:49:59 +00:00
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struct irq_2_iommu {
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2008-07-10 18:16:44 +00:00
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struct intel_iommu *iommu;
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u16 irte_index;
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u16 sub_handle;
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u8 irte_mask;
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2008-08-20 03:49:59 +00:00
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};
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2008-08-20 03:50:21 +00:00
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static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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2008-10-15 13:27:23 +00:00
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return (irq < nr_irqs) ?: irq_2_iommuX + irq : NULL;
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2008-08-20 03:50:21 +00:00
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}
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2008-10-15 13:27:23 +00:00
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2008-08-20 03:50:21 +00:00
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static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
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{
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return irq_2_iommu(irq);
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}
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2008-07-10 18:16:44 +00:00
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static DEFINE_SPINLOCK(irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
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2008-07-10 18:16:44 +00:00
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{
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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irq_iommu = irq_2_iommu(irq);
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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if (!irq_iommu)
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return NULL;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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if (!irq_iommu->iommu)
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return NULL;
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return irq_iommu;
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}
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int irq_remapped(int irq)
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{
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return valid_irq_2_iommu(irq) != NULL;
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2008-07-10 18:16:44 +00:00
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}
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int get_irte(int irq, struct irte *entry)
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{
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int index;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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if (!entry)
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2008-07-10 18:16:44 +00:00
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return -1;
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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*entry = *(irq_iommu->iommu->ir_table->base + index);
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return 0;
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}
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int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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struct ir_table *table = iommu->ir_table;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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u16 index, start_index;
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unsigned int mask = 0;
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int i;
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if (!count)
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return -1;
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2008-08-20 03:50:21 +00:00
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/* protect irq_2_iommu_alloc later */
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if (irq >= nr_irqs)
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return -1;
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2008-07-10 18:16:44 +00:00
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/*
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* start the IRTE search from index 0.
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*/
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index = start_index = 0;
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if (count > 1) {
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count = __roundup_pow_of_two(count);
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mask = ilog2(count);
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}
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if (mask > ecap_max_handle_mask(iommu->ecap)) {
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printk(KERN_ERR
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"Requested mask %x exceeds the max invalidation handle"
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" mask value %Lx\n", mask,
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ecap_max_handle_mask(iommu->ecap));
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return -1;
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}
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spin_lock(&irq_2_ir_lock);
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do {
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for (i = index; i < index + count; i++)
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if (table->base[i].present)
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break;
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/* empty index found */
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if (i == index + count)
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break;
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index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
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if (index == start_index) {
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spin_unlock(&irq_2_ir_lock);
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printk(KERN_ERR "can't allocate an IRTE\n");
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return -1;
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}
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} while (1);
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for (i = index; i < index + count; i++)
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table->base[i].present = 1;
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2008-08-20 03:50:21 +00:00
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irq_iommu = irq_2_iommu_alloc(irq);
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = mask;
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return index;
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}
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static void qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
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{
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struct qi_desc desc;
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desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
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| QI_IEC_SELECTIVE;
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desc.high = 0;
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qi_submit_sync(&desc, iommu);
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}
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int map_irq_to_irte_handle(int irq, u16 *sub_handle)
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{
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int index;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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*sub_handle = irq_iommu->sub_handle;
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index = irq_iommu->irte_index;
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return index;
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}
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int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
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{
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-21 00:22:51 +00:00
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irq_iommu = irq_2_iommu_alloc(irq);
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = subhandle;
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irq_iommu->irte_mask = 0;
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return 0;
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}
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int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
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{
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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irq_iommu->iommu = NULL;
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irq_iommu->irte_index = 0;
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irq_iommu->sub_handle = 0;
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irq_2_iommu(irq)->irte_mask = 0;
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return 0;
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}
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int modify_irte(int irq, struct irte *irte_modified)
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{
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int index;
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struct irte *irte;
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struct intel_iommu *iommu;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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iommu = irq_iommu->iommu;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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2008-07-10 18:16:44 +00:00
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irte = &iommu->ir_table->base[index];
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set_64bit((unsigned long *)irte, irte_modified->low | (1 << 1));
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__iommu_flush_cache(iommu, irte, sizeof(*irte));
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qi_flush_iec(iommu, index, 0);
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spin_unlock(&irq_2_ir_lock);
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return 0;
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}
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int flush_irte(int irq)
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{
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int index;
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struct intel_iommu *iommu;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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iommu = irq_iommu->iommu;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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qi_flush_iec(iommu, index, irq_iommu->irte_mask);
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return 0;
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}
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x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10 18:16:56 +00:00
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struct intel_iommu *map_ioapic_to_ir(int apic)
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{
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int i;
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for (i = 0; i < MAX_IO_APICS; i++)
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if (ir_ioapic[i].id == apic)
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return ir_ioapic[i].iommu;
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return NULL;
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}
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2008-07-10 18:16:57 +00:00
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struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd;
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drhd = dmar_find_matched_drhd_unit(dev);
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if (!drhd)
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return NULL;
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return drhd->iommu;
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}
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2008-07-10 18:16:44 +00:00
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int free_irte(int irq)
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{
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int index, i;
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struct irte *irte;
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struct intel_iommu *iommu;
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2008-08-20 03:50:21 +00:00
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struct irq_2_iommu *irq_iommu;
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2008-07-10 18:16:44 +00:00
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spin_lock(&irq_2_ir_lock);
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2008-08-20 03:50:21 +00:00
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irq_iommu = valid_irq_2_iommu(irq);
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if (!irq_iommu) {
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2008-07-10 18:16:44 +00:00
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spin_unlock(&irq_2_ir_lock);
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return -1;
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}
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2008-08-20 03:50:21 +00:00
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iommu = irq_iommu->iommu;
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2008-07-10 18:16:44 +00:00
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2008-08-20 03:50:21 +00:00
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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2008-07-10 18:16:44 +00:00
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irte = &iommu->ir_table->base[index];
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2008-08-20 03:50:21 +00:00
|
|
|
if (!irq_iommu->sub_handle) {
|
|
|
|
for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
|
2008-07-10 18:16:44 +00:00
|
|
|
set_64bit((unsigned long *)irte, 0);
|
2008-08-20 03:50:21 +00:00
|
|
|
qi_flush_iec(iommu, index, irq_iommu->irte_mask);
|
2008-07-10 18:16:44 +00:00
|
|
|
}
|
|
|
|
|
2008-08-20 03:50:21 +00:00
|
|
|
irq_iommu->iommu = NULL;
|
|
|
|
irq_iommu->irte_index = 0;
|
|
|
|
irq_iommu->sub_handle = 0;
|
|
|
|
irq_iommu->irte_mask = 0;
|
2008-07-10 18:16:44 +00:00
|
|
|
|
|
|
|
spin_unlock(&irq_2_ir_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-10 18:16:43 +00:00
|
|
|
static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
|
|
|
|
{
|
|
|
|
u64 addr;
|
|
|
|
u32 cmd, sts;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
addr = virt_to_phys((void *)iommu->ir_table->base);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->register_lock, flags);
|
|
|
|
|
|
|
|
dmar_writeq(iommu->reg + DMAR_IRTA_REG,
|
|
|
|
(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
|
|
|
|
|
|
|
|
/* Set interrupt-remapping table pointer */
|
|
|
|
cmd = iommu->gcmd | DMA_GCMD_SIRTP;
|
|
|
|
writel(cmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
|
|
readl, (sts & DMA_GSTS_IRTPS), sts);
|
|
|
|
spin_unlock_irqrestore(&iommu->register_lock, flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* global invalidation of interrupt entry cache before enabling
|
|
|
|
* interrupt-remapping.
|
|
|
|
*/
|
|
|
|
qi_global_iec(iommu);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&iommu->register_lock, flags);
|
|
|
|
|
|
|
|
/* Enable interrupt-remapping */
|
|
|
|
cmd = iommu->gcmd | DMA_GCMD_IRE;
|
|
|
|
iommu->gcmd |= DMA_GCMD_IRE;
|
|
|
|
writel(cmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
|
|
readl, (sts & DMA_GSTS_IRES), sts);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&iommu->register_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
|
|
|
|
{
|
|
|
|
struct ir_table *ir_table;
|
|
|
|
struct page *pages;
|
|
|
|
|
|
|
|
ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!iommu->ir_table)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
|
|
|
|
|
|
|
|
if (!pages) {
|
|
|
|
printk(KERN_ERR "failed to allocate pages of order %d\n",
|
|
|
|
INTR_REMAP_PAGE_ORDER);
|
|
|
|
kfree(iommu->ir_table);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
ir_table->base = page_address(pages);
|
|
|
|
|
|
|
|
iommu_set_intr_remapping(iommu, mode);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __init enable_intr_remapping(int eim)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
int setup = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* check for the Interrupt-remapping support
|
|
|
|
*/
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (eim && !ecap_eim_support(iommu->ecap)) {
|
|
|
|
printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
|
|
|
|
" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable queued invalidation for all the DRHD's.
|
|
|
|
*/
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
|
|
int ret;
|
|
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
ret = dmar_enable_qi(iommu);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
|
|
|
|
" invalidation, ecap %Lx, ret %d\n",
|
|
|
|
drhd->reg_base_addr, iommu->ecap, ret);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
|
|
*/
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (setup_intr_remapping(iommu, eim))
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
setup = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!setup)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
intr_remapping_enabled = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
/*
|
|
|
|
* handle error condition gracefully here!
|
|
|
|
*/
|
|
|
|
return -1;
|
|
|
|
}
|
2008-07-10 18:16:40 +00:00
|
|
|
|
|
|
|
static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
|
|
|
|
struct intel_iommu *iommu)
|
|
|
|
{
|
|
|
|
struct acpi_dmar_hardware_unit *drhd;
|
|
|
|
struct acpi_dmar_device_scope *scope;
|
|
|
|
void *start, *end;
|
|
|
|
|
|
|
|
drhd = (struct acpi_dmar_hardware_unit *)header;
|
|
|
|
|
|
|
|
start = (void *)(drhd + 1);
|
|
|
|
end = ((void *)drhd) + header->length;
|
|
|
|
|
|
|
|
while (start < end) {
|
|
|
|
scope = start;
|
|
|
|
if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
|
|
|
|
if (ir_ioapic_num == MAX_IO_APICS) {
|
|
|
|
printk(KERN_WARNING "Exceeded Max IO APICS\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
printk(KERN_INFO "IOAPIC id %d under DRHD base"
|
|
|
|
" 0x%Lx\n", scope->enumeration_id,
|
|
|
|
drhd->address);
|
|
|
|
|
|
|
|
ir_ioapic[ir_ioapic_num].iommu = iommu;
|
|
|
|
ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
|
|
|
|
ir_ioapic_num++;
|
|
|
|
}
|
|
|
|
start += scope->length;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Finds the assocaition between IOAPIC's and its Interrupt-remapping
|
|
|
|
* hardware unit.
|
|
|
|
*/
|
|
|
|
int __init parse_ioapics_under_ir(void)
|
|
|
|
{
|
|
|
|
struct dmar_drhd_unit *drhd;
|
|
|
|
int ir_supported = 0;
|
|
|
|
|
|
|
|
for_each_drhd_unit(drhd) {
|
|
|
|
struct intel_iommu *iommu = drhd->iommu;
|
|
|
|
|
|
|
|
if (ecap_ir_support(iommu->ecap)) {
|
|
|
|
if (ir_parse_ioapic_scope(drhd->hdr, iommu))
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
ir_supported = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ir_supported && ir_ioapic_num != nr_ioapics) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Not all IO-APIC's listed under remapping hardware\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ir_supported;
|
|
|
|
}
|