2011-04-28 17:28:08 +00:00
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/*
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* sh7372 Power management support
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*
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* Copyright (C) 2011 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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2011-04-28 17:39:32 +00:00
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#include <linux/cpuidle.h>
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2011-04-28 17:28:08 +00:00
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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2011-08-25 13:34:19 +00:00
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#include <linux/pm_clock.h>
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2011-07-01 20:13:56 +00:00
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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2011-04-28 17:28:08 +00:00
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <mach/common.h>
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2011-07-01 20:13:56 +00:00
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#include <mach/sh7372.h>
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2011-04-28 17:28:08 +00:00
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#define SMFRAM 0xe6a70000
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#define SYSTBCR 0xe6150024
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#define SBAR 0xe6180020
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#define APARMBAREA 0xe6f10020
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2011-07-01 20:13:56 +00:00
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#define SPDCR 0xe6180008
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#define SWUCR 0xe6180014
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#define PSTR 0xe6180080
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#define PSTR_RETRIES 100
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#define PSTR_DELAY_US 10
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#ifdef CONFIG_PM
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static int pd_power_down(struct generic_pm_domain *genpd)
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{
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struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
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unsigned int mask = 1 << sh7372_pd->bit_shift;
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if (__raw_readl(PSTR) & mask) {
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unsigned int retry_count;
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__raw_writel(mask, SPDCR);
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for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
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if (!(__raw_readl(SPDCR) & mask))
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break;
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cpu_relax();
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}
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}
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pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
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mask, __raw_readl(PSTR));
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return 0;
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}
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static int pd_power_up(struct generic_pm_domain *genpd)
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{
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struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
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unsigned int mask = 1 << sh7372_pd->bit_shift;
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unsigned int retry_count;
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int ret = 0;
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if (__raw_readl(PSTR) & mask)
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goto out;
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__raw_writel(mask, SWUCR);
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for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
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if (!(__raw_readl(SWUCR) & mask))
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goto out;
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if (retry_count > PSTR_RETRIES)
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udelay(PSTR_DELAY_US);
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else
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cpu_relax();
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}
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if (__raw_readl(SWUCR) & mask)
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ret = -EIO;
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out:
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pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
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mask, __raw_readl(PSTR));
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return ret;
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}
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static bool pd_active_wakeup(struct device *dev)
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{
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return true;
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}
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void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
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{
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struct generic_pm_domain *genpd = &sh7372_pd->genpd;
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pm_genpd_init(genpd, NULL, false);
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genpd->stop_device = pm_clk_suspend;
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genpd->start_device = pm_clk_resume;
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2011-08-25 13:37:04 +00:00
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genpd->dev_irq_safe = true;
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2011-07-01 20:13:56 +00:00
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genpd->active_wakeup = pd_active_wakeup;
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2011-08-14 11:35:39 +00:00
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genpd->power_off = pd_power_down;
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genpd->power_on = pd_power_up;
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2011-07-10 08:39:32 +00:00
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genpd->power_on(&sh7372_pd->genpd);
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2011-07-01 20:13:56 +00:00
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}
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void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
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struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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pm_genpd_add_device(&sh7372_pd->genpd, dev);
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2011-08-25 13:34:12 +00:00
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if (pm_clk_no_clocks(dev))
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pm_clk_add(dev, NULL);
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2011-07-01 20:13:56 +00:00
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}
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2011-08-14 11:35:39 +00:00
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void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
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struct sh7372_pm_domain *sh7372_sd)
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{
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pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
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}
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2011-07-01 20:13:56 +00:00
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struct sh7372_pm_domain sh7372_a4lc = {
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.bit_shift = 1,
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};
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2011-07-10 08:12:08 +00:00
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struct sh7372_pm_domain sh7372_a4mp = {
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.bit_shift = 2,
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};
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2011-07-10 08:38:22 +00:00
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struct sh7372_pm_domain sh7372_d4 = {
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.bit_shift = 3,
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};
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2011-07-01 20:14:45 +00:00
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struct sh7372_pm_domain sh7372_a3rv = {
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.bit_shift = 6,
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};
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2011-07-01 20:14:53 +00:00
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struct sh7372_pm_domain sh7372_a3ri = {
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.bit_shift = 8,
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};
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2011-07-01 20:15:01 +00:00
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struct sh7372_pm_domain sh7372_a3sg = {
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.bit_shift = 13,
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};
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2011-07-01 20:13:56 +00:00
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#endif /* CONFIG_PM */
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2011-05-25 02:22:58 +00:00
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static void sh7372_enter_core_standby(void)
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2011-04-28 17:28:08 +00:00
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{
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void __iomem *smfram = (void __iomem *)SMFRAM;
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__raw_writel(0, APARMBAREA); /* translate 4k */
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__raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
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__raw_writel(0x10, SYSTBCR); /* enable core standby */
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__raw_writel(0, smfram + 0x3c); /* clear page table address */
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sh7372_cpu_suspend();
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cpu_init();
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/* if page table address is non-NULL then we have been powered down */
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if (__raw_readl(smfram + 0x3c)) {
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__raw_writel(__raw_readl(smfram + 0x40),
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__va(__raw_readl(smfram + 0x3c)));
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flush_tlb_all();
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set_cr(__raw_readl(smfram + 0x38));
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}
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__raw_writel(0, SYSTBCR); /* disable core standby */
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__raw_writel(0, SBAR); /* disable reset vector translation */
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}
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2011-04-28 17:39:32 +00:00
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#ifdef CONFIG_CPU_IDLE
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static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
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{
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struct cpuidle_state *state;
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int i = dev->state_count;
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state = &dev->states[i];
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snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
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strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
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state->exit_latency = 10;
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state->target_residency = 20 + 10;
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state->power_usage = 1; /* perhaps not */
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state->flags = 0;
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state->flags |= CPUIDLE_FLAG_TIME_VALID;
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shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
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dev->state_count = i + 1;
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}
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static void sh7372_cpuidle_init(void)
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{
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shmobile_cpuidle_setup = sh7372_cpuidle_setup;
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}
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#else
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static void sh7372_cpuidle_init(void) {}
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#endif
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#ifdef CONFIG_SUSPEND
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2011-04-28 17:28:08 +00:00
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static int sh7372_enter_suspend(suspend_state_t suspend_state)
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{
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sh7372_enter_core_standby();
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return 0;
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}
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static void sh7372_suspend_init(void)
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{
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shmobile_suspend_ops.enter = sh7372_enter_suspend;
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}
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#else
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static void sh7372_suspend_init(void) {}
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#endif
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#define DBGREG1 0xe6100020
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#define DBGREG9 0xe6100040
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void __init sh7372_pm_init(void)
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{
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/* enable DBG hardware block to kick SYSC */
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__raw_writel(0x0000a500, DBGREG9);
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__raw_writel(0x0000a501, DBGREG9);
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__raw_writel(0x00000000, DBGREG1);
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sh7372_suspend_init();
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2011-04-28 17:39:32 +00:00
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sh7372_cpuidle_init();
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2011-04-28 17:28:08 +00:00
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}
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