736 lines
20 KiB
C
736 lines
20 KiB
C
![]() |
/*
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* ohci-omap3.c - driver for OHCI on OMAP3 and later processors
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*
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* Bus Glue for OMAP3 USBHOST 3 port OHCI controller
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* This controller is also used in later OMAPs and AM35x chips
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*
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* Copyright (C) 2007-2010 Texas Instruments, Inc.
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* Author: Vikram Pandita <vikram.pandita@ti.com>
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* Author: Anand Gadiyar <gadiyar@ti.com>
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*
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* Based on ehci-omap.c and some other ohci glue layers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* TODO (last updated Mar 10th, 2010):
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* - add kernel-doc
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* - Factor out code common to EHCI to a separate file
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* - Make EHCI and OHCI coexist together
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* - needs newer silicon versions to actually work
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* - the last one to be loaded currently steps on the other's toes
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* - Add hooks for configuring transceivers, etc. at init/exit
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* - Add aggressive clock-management code
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*/
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <plat/usb.h>
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/*
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* OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
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* Use ohci_omap_readl()/ohci_omap_writel() functions
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*/
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/* TLL Register Set */
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#define OMAP_USBTLL_REVISION (0x00)
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#define OMAP_USBTLL_SYSCONFIG (0x10)
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#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
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#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
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#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
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#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP_USBTLL_SYSSTATUS (0x14)
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#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
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#define OMAP_USBTLL_IRQSTATUS (0x18)
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#define OMAP_USBTLL_IRQENABLE (0x1C)
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#define OMAP_TLL_SHARED_CONF (0x30)
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#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
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#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
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#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
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#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
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#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
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#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
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#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
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#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
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#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
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#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
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#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
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#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
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#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
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#define OMAP_TLL_CHANNEL_COUNT 3
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/* UHH Register Set */
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#define OMAP_UHH_REVISION (0x00)
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#define OMAP_UHH_SYSCONFIG (0x10)
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#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
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#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
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#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
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#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
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#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP_UHH_SYSSTATUS (0x14)
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#define OMAP_UHH_SYSSTATUS_UHHRESETDONE (1 << 0)
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#define OMAP_UHH_SYSSTATUS_OHCIRESETDONE (1 << 1)
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#define OMAP_UHH_SYSSTATUS_EHCIRESETDONE (1 << 2)
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#define OMAP_UHH_HOSTCONFIG (0x40)
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#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
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#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
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#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
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#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
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#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
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#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
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#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
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#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
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#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
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#define OMAP_UHH_DEBUG_CSR (0x44)
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/*-------------------------------------------------------------------------*/
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static inline void ohci_omap_writel(void __iomem *base, u32 reg, u32 val)
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{
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__raw_writel(val, base + reg);
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}
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static inline u32 ohci_omap_readl(void __iomem *base, u32 reg)
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{
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return __raw_readl(base + reg);
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}
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static inline void ohci_omap_writeb(void __iomem *base, u8 reg, u8 val)
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{
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__raw_writeb(val, base + reg);
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}
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static inline u8 ohci_omap_readb(void __iomem *base, u8 reg)
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{
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return __raw_readb(base + reg);
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}
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/*-------------------------------------------------------------------------*/
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struct ohci_hcd_omap3 {
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struct ohci_hcd *ohci;
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struct device *dev;
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struct clk *usbhost_ick;
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struct clk *usbhost2_120m_fck;
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struct clk *usbhost1_48m_fck;
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struct clk *usbtll_fck;
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struct clk *usbtll_ick;
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/* port_mode: TLL/PHY, 2/3/4/6-PIN, DP-DM/DAT-SE0 */
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enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS];
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void __iomem *uhh_base;
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void __iomem *tll_base;
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void __iomem *ohci_base;
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unsigned es2_compatibility:1;
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};
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/*-------------------------------------------------------------------------*/
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static void ohci_omap3_clock_power(struct ohci_hcd_omap3 *omap, int on)
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{
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if (on) {
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clk_enable(omap->usbtll_ick);
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clk_enable(omap->usbtll_fck);
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clk_enable(omap->usbhost_ick);
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clk_enable(omap->usbhost1_48m_fck);
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clk_enable(omap->usbhost2_120m_fck);
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} else {
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clk_disable(omap->usbhost2_120m_fck);
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clk_disable(omap->usbhost1_48m_fck);
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clk_disable(omap->usbhost_ick);
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clk_disable(omap->usbtll_fck);
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clk_disable(omap->usbtll_ick);
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}
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}
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static int ohci_omap3_init(struct usb_hcd *hcd)
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{
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dev_dbg(hcd->self.controller, "starting OHCI controller\n");
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return ohci_init(hcd_to_ohci(hcd));
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}
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/*-------------------------------------------------------------------------*/
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static int ohci_omap3_start(struct usb_hcd *hcd)
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{
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struct ohci_hcd *ohci = hcd_to_ohci(hcd);
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int ret;
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/*
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* RemoteWakeupConnected has to be set explicitly before
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* calling ohci_run. The reset value of RWC is 0.
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*/
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ohci->hc_control = OHCI_CTRL_RWC;
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writel(OHCI_CTRL_RWC, &ohci->regs->control);
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ret = ohci_run(ohci);
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if (ret < 0) {
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dev_err(hcd->self.controller, "can't start\n");
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ohci_stop(hcd);
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}
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return ret;
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}
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/*-------------------------------------------------------------------------*/
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/*
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* convert the port-mode enum to a value we can use in the FSLSMODE
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* field of USBTLL_CHANNEL_CONF
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*/
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static unsigned ohci_omap3_fslsmode(enum ohci_omap3_port_mode mode)
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{
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switch (mode) {
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case OMAP_OHCI_PORT_MODE_UNUSED:
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case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
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return 0x0;
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case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
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return 0x1;
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case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
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return 0x2;
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case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
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return 0x3;
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case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
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return 0x4;
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case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
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return 0x5;
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case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
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return 0x6;
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case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
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return 0x7;
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case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
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return 0xA;
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case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
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return 0xB;
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default:
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pr_warning("Invalid port mode, using default\n");
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return 0x0;
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}
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}
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static void ohci_omap3_tll_config(struct ohci_hcd_omap3 *omap)
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{
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u32 reg;
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int i;
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/* Program TLL SHARED CONF */
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reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
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reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
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reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
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reg |= OMAP_TLL_SHARED_CONF_USB_DIVRATION;
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reg |= OMAP_TLL_SHARED_CONF_FCLK_IS_ON;
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ohci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
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/* Program each TLL channel */
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/*
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* REVISIT: Only the 3-pin and 4-pin PHY modes have
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* actually been tested.
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*/
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for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
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/* Enable only those channels that are actually used */
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if (omap->port_mode[i] == OMAP_OHCI_PORT_MODE_UNUSED)
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continue;
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reg = ohci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
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reg |= ohci_omap3_fslsmode(omap->port_mode[i])
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<< OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
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reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
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reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
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ohci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
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}
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}
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/* omap3_start_ohci
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* - Start the TI USBHOST controller
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*/
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static int omap3_start_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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u32 reg = 0;
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int ret = 0;
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dev_dbg(omap->dev, "starting TI OHCI USB Controller\n");
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/* Get all the clock handles we need */
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omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
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if (IS_ERR(omap->usbhost_ick)) {
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dev_err(omap->dev, "could not get usbhost_ick\n");
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ret = PTR_ERR(omap->usbhost_ick);
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goto err_host_ick;
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}
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omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
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if (IS_ERR(omap->usbhost2_120m_fck)) {
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dev_err(omap->dev, "could not get usbhost_120m_fck\n");
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ret = PTR_ERR(omap->usbhost2_120m_fck);
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goto err_host_120m_fck;
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}
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omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
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if (IS_ERR(omap->usbhost1_48m_fck)) {
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dev_err(omap->dev, "could not get usbhost_48m_fck\n");
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ret = PTR_ERR(omap->usbhost1_48m_fck);
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goto err_host_48m_fck;
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}
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omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
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if (IS_ERR(omap->usbtll_fck)) {
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dev_err(omap->dev, "could not get usbtll_fck\n");
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ret = PTR_ERR(omap->usbtll_fck);
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goto err_tll_fck;
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}
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|
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omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
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if (IS_ERR(omap->usbtll_ick)) {
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dev_err(omap->dev, "could not get usbtll_ick\n");
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ret = PTR_ERR(omap->usbtll_ick);
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goto err_tll_ick;
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}
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|
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/* Now enable all the clocks in the correct order */
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ohci_omap3_clock_power(omap, 1);
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|
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/* perform TLL soft reset, and wait until reset is complete */
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ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
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OMAP_USBTLL_SYSCONFIG_SOFTRESET);
|
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|
|
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/* Wait for TLL reset to complete */
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while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
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& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
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cpu_relax();
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if (time_after(jiffies, timeout)) {
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dev_dbg(omap->dev, "operation timed out\n");
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ret = -EINVAL;
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goto err_sys_status;
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}
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||
|
}
|
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|
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dev_dbg(omap->dev, "TLL reset done\n");
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|
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/* (1<<3) = no idle mode only for initial debugging */
|
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ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
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OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
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OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
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OMAP_USBTLL_SYSCONFIG_CACTIVITY);
|
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|
|
||
|
|
||
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/* Put UHH in NoIdle/NoStandby mode */
|
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reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
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reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
|
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|
| OMAP_UHH_SYSCONFIG_SIDLEMODE
|
||
|
| OMAP_UHH_SYSCONFIG_CACTIVITY
|
||
|
| OMAP_UHH_SYSCONFIG_MIDLEMODE);
|
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reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
|
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reg &= ~OMAP_UHH_SYSCONFIG_SOFTRESET;
|
||
|
|
||
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ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
|
||
|
|
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reg = ohci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
|
||
|
|
||
|
/* setup ULPI bypass and burst configurations */
|
||
|
reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
|
||
|
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
|
||
|
| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
|
||
|
|
||
|
/*
|
||
|
* REVISIT: Pi_CONNECT_STATUS controls MStandby
|
||
|
* assertion and Swakeup generation - let us not
|
||
|
* worry about this for now. OMAP HWMOD framework
|
||
|
* might take care of this later. If not, we can
|
||
|
* update these registers when adding aggressive
|
||
|
* clock management code.
|
||
|
*
|
||
|
* For now, turn off all the Pi_CONNECT_STATUS bits
|
||
|
*
|
||
|
if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
|
||
|
if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
|
||
|
if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
|
||
|
*/
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
|
||
|
|
||
|
if (omap->es2_compatibility) {
|
||
|
/*
|
||
|
* All OHCI modes need to go through the TLL,
|
||
|
* unlike in the EHCI case. So use UTMI mode
|
||
|
* for all ports for OHCI, on ES2.x silicon
|
||
|
*/
|
||
|
dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
|
||
|
reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
|
||
|
} else {
|
||
|
dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
|
||
|
if (omap->port_mode[0] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
|
||
|
else
|
||
|
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
|
||
|
|
||
|
if (omap->port_mode[1] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
|
||
|
else
|
||
|
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
|
||
|
|
||
|
if (omap->port_mode[2] == OMAP_OHCI_PORT_MODE_UNUSED)
|
||
|
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
|
||
|
else
|
||
|
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
|
||
|
|
||
|
}
|
||
|
ohci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
|
||
|
dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
|
||
|
|
||
|
ohci_omap3_tll_config(omap);
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
err_sys_status:
|
||
|
ohci_omap3_clock_power(omap, 0);
|
||
|
clk_put(omap->usbtll_ick);
|
||
|
|
||
|
err_tll_ick:
|
||
|
clk_put(omap->usbtll_fck);
|
||
|
|
||
|
err_tll_fck:
|
||
|
clk_put(omap->usbhost1_48m_fck);
|
||
|
|
||
|
err_host_48m_fck:
|
||
|
clk_put(omap->usbhost2_120m_fck);
|
||
|
|
||
|
err_host_120m_fck:
|
||
|
clk_put(omap->usbhost_ick);
|
||
|
|
||
|
err_host_ick:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static void omap3_stop_ohci(struct ohci_hcd_omap3 *omap, struct usb_hcd *hcd)
|
||
|
{
|
||
|
unsigned long timeout = jiffies + msecs_to_jiffies(100);
|
||
|
|
||
|
dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
|
||
|
|
||
|
/* Reset USBHOST for insmod/rmmod to work */
|
||
|
ohci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
|
||
|
OMAP_UHH_SYSCONFIG_SOFTRESET);
|
||
|
while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
|
||
|
& OMAP_UHH_SYSSTATUS_UHHRESETDONE)) {
|
||
|
cpu_relax();
|
||
|
|
||
|
if (time_after(jiffies, timeout))
|
||
|
dev_dbg(omap->dev, "operation timed out\n");
|
||
|
}
|
||
|
|
||
|
while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
|
||
|
& OMAP_UHH_SYSSTATUS_OHCIRESETDONE)) {
|
||
|
cpu_relax();
|
||
|
|
||
|
if (time_after(jiffies, timeout))
|
||
|
dev_dbg(omap->dev, "operation timed out\n");
|
||
|
}
|
||
|
|
||
|
while (!(ohci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
|
||
|
& OMAP_UHH_SYSSTATUS_EHCIRESETDONE)) {
|
||
|
cpu_relax();
|
||
|
|
||
|
if (time_after(jiffies, timeout))
|
||
|
dev_dbg(omap->dev, "operation timed out\n");
|
||
|
}
|
||
|
|
||
|
ohci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
|
||
|
|
||
|
while (!(ohci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
|
||
|
& (1 << 0))) {
|
||
|
cpu_relax();
|
||
|
|
||
|
if (time_after(jiffies, timeout))
|
||
|
dev_dbg(omap->dev, "operation timed out\n");
|
||
|
}
|
||
|
|
||
|
ohci_omap3_clock_power(omap, 0);
|
||
|
|
||
|
if (omap->usbtll_fck != NULL) {
|
||
|
clk_put(omap->usbtll_fck);
|
||
|
omap->usbtll_fck = NULL;
|
||
|
}
|
||
|
|
||
|
if (omap->usbhost_ick != NULL) {
|
||
|
clk_put(omap->usbhost_ick);
|
||
|
omap->usbhost_ick = NULL;
|
||
|
}
|
||
|
|
||
|
if (omap->usbhost1_48m_fck != NULL) {
|
||
|
clk_put(omap->usbhost1_48m_fck);
|
||
|
omap->usbhost1_48m_fck = NULL;
|
||
|
}
|
||
|
|
||
|
if (omap->usbhost2_120m_fck != NULL) {
|
||
|
clk_put(omap->usbhost2_120m_fck);
|
||
|
omap->usbhost2_120m_fck = NULL;
|
||
|
}
|
||
|
|
||
|
if (omap->usbtll_ick != NULL) {
|
||
|
clk_put(omap->usbtll_ick);
|
||
|
omap->usbtll_ick = NULL;
|
||
|
}
|
||
|
|
||
|
dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
|
||
|
}
|
||
|
|
||
|
/*-------------------------------------------------------------------------*/
|
||
|
|
||
|
static const struct hc_driver ohci_omap3_hc_driver = {
|
||
|
.description = hcd_name,
|
||
|
.product_desc = "OMAP3 OHCI Host Controller",
|
||
|
.hcd_priv_size = sizeof(struct ohci_hcd),
|
||
|
|
||
|
/*
|
||
|
* generic hardware linkage
|
||
|
*/
|
||
|
.irq = ohci_irq,
|
||
|
.flags = HCD_USB11 | HCD_MEMORY,
|
||
|
|
||
|
/*
|
||
|
* basic lifecycle operations
|
||
|
*/
|
||
|
.reset = ohci_omap3_init,
|
||
|
.start = ohci_omap3_start,
|
||
|
.stop = ohci_stop,
|
||
|
.shutdown = ohci_shutdown,
|
||
|
|
||
|
/*
|
||
|
* managing i/o requests and associated device resources
|
||
|
*/
|
||
|
.urb_enqueue = ohci_urb_enqueue,
|
||
|
.urb_dequeue = ohci_urb_dequeue,
|
||
|
.endpoint_disable = ohci_endpoint_disable,
|
||
|
|
||
|
/*
|
||
|
* scheduling support
|
||
|
*/
|
||
|
.get_frame_number = ohci_get_frame,
|
||
|
|
||
|
/*
|
||
|
* root hub support
|
||
|
*/
|
||
|
.hub_status_data = ohci_hub_status_data,
|
||
|
.hub_control = ohci_hub_control,
|
||
|
#ifdef CONFIG_PM
|
||
|
.bus_suspend = ohci_bus_suspend,
|
||
|
.bus_resume = ohci_bus_resume,
|
||
|
#endif
|
||
|
.start_port_reset = ohci_start_port_reset,
|
||
|
};
|
||
|
|
||
|
/*-------------------------------------------------------------------------*/
|
||
|
|
||
|
/*
|
||
|
* configure so an HC device and id are always provided
|
||
|
* always called with process context; sleeping is OK
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* ohci_hcd_omap3_probe - initialize OMAP-based HCDs
|
||
|
*
|
||
|
* Allocates basic resources for this USB host controller, and
|
||
|
* then invokes the start() method for the HCD associated with it
|
||
|
* through the hotplug entry's driver_data.
|
||
|
*/
|
||
|
static int __devinit ohci_hcd_omap3_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct ohci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
|
||
|
struct ohci_hcd_omap3 *omap;
|
||
|
struct resource *res;
|
||
|
struct usb_hcd *hcd;
|
||
|
int ret = -ENODEV;
|
||
|
int irq;
|
||
|
|
||
|
if (usb_disabled())
|
||
|
goto err_disabled;
|
||
|
|
||
|
if (!pdata) {
|
||
|
dev_dbg(&pdev->dev, "missing platform_data\n");
|
||
|
goto err_pdata;
|
||
|
}
|
||
|
|
||
|
irq = platform_get_irq(pdev, 0);
|
||
|
|
||
|
omap = kzalloc(sizeof(*omap), GFP_KERNEL);
|
||
|
if (!omap) {
|
||
|
ret = -ENOMEM;
|
||
|
goto err_disabled;
|
||
|
}
|
||
|
|
||
|
hcd = usb_create_hcd(&ohci_omap3_hc_driver, &pdev->dev,
|
||
|
dev_name(&pdev->dev));
|
||
|
if (!hcd) {
|
||
|
ret = -ENOMEM;
|
||
|
goto err_create_hcd;
|
||
|
}
|
||
|
|
||
|
platform_set_drvdata(pdev, omap);
|
||
|
omap->dev = &pdev->dev;
|
||
|
omap->port_mode[0] = pdata->port_mode[0];
|
||
|
omap->port_mode[1] = pdata->port_mode[1];
|
||
|
omap->port_mode[2] = pdata->port_mode[2];
|
||
|
omap->es2_compatibility = pdata->es2_compatibility;
|
||
|
omap->ohci = hcd_to_ohci(hcd);
|
||
|
|
||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
||
|
hcd->rsrc_start = res->start;
|
||
|
hcd->rsrc_len = resource_size(res);
|
||
|
|
||
|
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
|
||
|
if (!hcd->regs) {
|
||
|
dev_err(&pdev->dev, "OHCI ioremap failed\n");
|
||
|
ret = -ENOMEM;
|
||
|
goto err_ioremap;
|
||
|
}
|
||
|
|
||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||
|
omap->uhh_base = ioremap(res->start, resource_size(res));
|
||
|
if (!omap->uhh_base) {
|
||
|
dev_err(&pdev->dev, "UHH ioremap failed\n");
|
||
|
ret = -ENOMEM;
|
||
|
goto err_uhh_ioremap;
|
||
|
}
|
||
|
|
||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||
|
omap->tll_base = ioremap(res->start, resource_size(res));
|
||
|
if (!omap->tll_base) {
|
||
|
dev_err(&pdev->dev, "TLL ioremap failed\n");
|
||
|
ret = -ENOMEM;
|
||
|
goto err_tll_ioremap;
|
||
|
}
|
||
|
|
||
|
ret = omap3_start_ohci(omap, hcd);
|
||
|
if (ret) {
|
||
|
dev_dbg(&pdev->dev, "failed to start ehci\n");
|
||
|
goto err_start;
|
||
|
}
|
||
|
|
||
|
ohci_hcd_init(omap->ohci);
|
||
|
|
||
|
ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
|
||
|
if (ret) {
|
||
|
dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
|
||
|
goto err_add_hcd;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
err_add_hcd:
|
||
|
omap3_stop_ohci(omap, hcd);
|
||
|
|
||
|
err_start:
|
||
|
iounmap(omap->tll_base);
|
||
|
|
||
|
err_tll_ioremap:
|
||
|
iounmap(omap->uhh_base);
|
||
|
|
||
|
err_uhh_ioremap:
|
||
|
iounmap(hcd->regs);
|
||
|
|
||
|
err_ioremap:
|
||
|
usb_put_hcd(hcd);
|
||
|
|
||
|
err_create_hcd:
|
||
|
kfree(omap);
|
||
|
err_pdata:
|
||
|
err_disabled:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* may be called without controller electrically present
|
||
|
* may be called with controller, bus, and devices active
|
||
|
*/
|
||
|
|
||
|
/**
|
||
|
* ohci_hcd_omap3_remove - shutdown processing for OHCI HCDs
|
||
|
* @pdev: USB Host Controller being removed
|
||
|
*
|
||
|
* Reverses the effect of ohci_hcd_omap3_probe(), first invoking
|
||
|
* the HCD's stop() method. It is always called from a thread
|
||
|
* context, normally "rmmod", "apmd", or something similar.
|
||
|
*/
|
||
|
static int __devexit ohci_hcd_omap3_remove(struct platform_device *pdev)
|
||
|
{
|
||
|
struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev);
|
||
|
struct usb_hcd *hcd = ohci_to_hcd(omap->ohci);
|
||
|
|
||
|
usb_remove_hcd(hcd);
|
||
|
omap3_stop_ohci(omap, hcd);
|
||
|
iounmap(hcd->regs);
|
||
|
iounmap(omap->tll_base);
|
||
|
iounmap(omap->uhh_base);
|
||
|
usb_put_hcd(hcd);
|
||
|
kfree(omap);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void ohci_hcd_omap3_shutdown(struct platform_device *pdev)
|
||
|
{
|
||
|
struct ohci_hcd_omap3 *omap = platform_get_drvdata(pdev);
|
||
|
struct usb_hcd *hcd = ohci_to_hcd(omap->ohci);
|
||
|
|
||
|
if (hcd->driver->shutdown)
|
||
|
hcd->driver->shutdown(hcd);
|
||
|
}
|
||
|
|
||
|
static struct platform_driver ohci_hcd_omap3_driver = {
|
||
|
.probe = ohci_hcd_omap3_probe,
|
||
|
.remove = __devexit_p(ohci_hcd_omap3_remove),
|
||
|
.shutdown = ohci_hcd_omap3_shutdown,
|
||
|
.driver = {
|
||
|
.name = "ohci-omap3",
|
||
|
},
|
||
|
};
|
||
|
|
||
|
MODULE_ALIAS("platform:ohci-omap3");
|
||
|
MODULE_AUTHOR("Anand Gadiyar <gadiyar@ti.com>");
|