908 lines
60 KiB
Verilog
908 lines
60 KiB
Verilog
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`timescale 1 ns / 1 ps
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module ledmatrix_v1_0_M00_AXI #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Base address of targeted slave
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parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
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// Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
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parameter integer C_M_AXI_BURST_LEN = 16,
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// Thread ID Width
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parameter integer C_M_AXI_ID_WIDTH = 1,
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// Width of Address Bus
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parameter integer C_M_AXI_ADDR_WIDTH = 32,
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// Width of Data Bus
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parameter integer C_M_AXI_DATA_WIDTH = 32,
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// Width of User Write Address Bus
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parameter integer C_M_AXI_AWUSER_WIDTH = 0,
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// Width of User Read Address Bus
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parameter integer C_M_AXI_ARUSER_WIDTH = 0,
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// Width of User Write Data Bus
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parameter integer C_M_AXI_WUSER_WIDTH = 0,
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// Width of User Read Data Bus
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parameter integer C_M_AXI_RUSER_WIDTH = 0,
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// Width of User Response Bus
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parameter integer C_M_AXI_BUSER_WIDTH = 0
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)
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(
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// Users to add ports here
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// User ports ends
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// Do not modify the ports beyond this line
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// Initiate AXI transactions
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input wire INIT_AXI_TXN,
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// Asserts when transaction is complete
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output wire TXN_DONE,
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// Asserts when ERROR is detected
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output reg ERROR,
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// Global Clock Signal.
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input wire M_AXI_ACLK,
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// Global Reset Singal. This Signal is Active Low
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input wire M_AXI_ARESETN,
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// Master Interface Write Address ID
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output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
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// Master Interface Write Address
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output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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output wire [7 : 0] M_AXI_AWLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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output wire [2 : 0] M_AXI_AWSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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output wire [1 : 0] M_AXI_AWBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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output wire M_AXI_AWLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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output wire [3 : 0] M_AXI_AWCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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output wire [2 : 0] M_AXI_AWPROT,
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// Quality of Service, QoS identifier sent for each write transaction.
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output wire [3 : 0] M_AXI_AWQOS,
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// Optional User-defined signal in the write address channel.
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output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid write address and control information.
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output wire M_AXI_AWVALID,
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// Write address ready. This signal indicates that
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// the slave is ready to accept an address and associated control signals
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input wire M_AXI_AWREADY,
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// Master Interface Write Data.
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output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
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// Write strobes. This signal indicates which byte
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// lanes hold valid data. There is one write strobe
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// bit for each eight bits of the write data bus.
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output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
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// Write last. This signal indicates the last transfer in a write burst.
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output wire M_AXI_WLAST,
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// Optional User-defined signal in the write data channel.
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output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
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// Write valid. This signal indicates that valid write
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// data and strobes are available
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output wire M_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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input wire M_AXI_WREADY,
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// Master Interface Write Response.
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input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
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// Write response. This signal indicates the status of the write transaction.
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input wire [1 : 0] M_AXI_BRESP,
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// Optional User-defined signal in the write response channel
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input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
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// Write response valid. This signal indicates that the
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// channel is signaling a valid write response.
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input wire M_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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output wire M_AXI_BREADY,
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// Master Interface Read Address.
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output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
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// Read address. This signal indicates the initial
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// address of a read burst transaction.
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output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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output wire [7 : 0] M_AXI_ARLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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output wire [2 : 0] M_AXI_ARSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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output wire [1 : 0] M_AXI_ARBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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output wire M_AXI_ARLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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output wire [3 : 0] M_AXI_ARCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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output wire [2 : 0] M_AXI_ARPROT,
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// Quality of Service, QoS identifier sent for each read transaction
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output wire [3 : 0] M_AXI_ARQOS,
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// Optional User-defined signal in the read address channel.
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output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid read address and control information
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output wire M_AXI_ARVALID,
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// Read address ready. This signal indicates that
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// the slave is ready to accept an address and associated control signals
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input wire M_AXI_ARREADY,
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// Read ID tag. This signal is the identification tag
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// for the read data group of signals generated by the slave.
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input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
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// Master Read Data
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input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
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// Read response. This signal indicates the status of the read transfer
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input wire [1 : 0] M_AXI_RRESP,
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// Read last. This signal indicates the last transfer in a read burst
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input wire M_AXI_RLAST,
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// Optional User-defined signal in the read address channel.
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input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
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// Read valid. This signal indicates that the channel
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// is signaling the required read data.
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input wire M_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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output wire M_AXI_RREADY
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);
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// function called clogb2 that returns an integer which has the
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//value of the ceiling of the log base 2
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// function called clogb2 that returns an integer which has the
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// value of the ceiling of the log base 2.
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function integer clogb2 (input integer bit_depth);
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begin
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for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
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bit_depth = bit_depth >> 1;
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end
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endfunction
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// C_TRANSACTIONS_NUM is the width of the index counter for
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// number of write or read transaction.
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localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1);
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// Burst length for transactions, in C_M_AXI_DATA_WIDTHs.
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// Non-2^n lengths will eventually cause bursts across 4K address boundaries.
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localparam integer C_MASTER_LENGTH = 12;
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// total number of burst transfers is master length divided by burst length and burst size
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localparam integer C_NO_BURSTS_REQ = C_MASTER_LENGTH-clogb2((C_M_AXI_BURST_LEN*C_M_AXI_DATA_WIDTH/8)-1);
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// Example State machine to initialize counter, initialize write transactions,
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// initialize read transactions and comparison of read data with the
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// written data words.
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parameter [1:0] IDLE = 2'b00, // This state initiates AXI4Lite transaction
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// after the state machine changes state to INIT_WRITE
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// when there is 0 to 1 transition on INIT_AXI_TXN
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INIT_WRITE = 2'b01, // This state initializes write transaction,
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// once writes are done, the state machine
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// changes state to INIT_READ
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INIT_READ = 2'b10, // This state initializes read transaction
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// once reads are done, the state machine
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// changes state to INIT_COMPARE
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INIT_COMPARE = 2'b11; // This state issues the status of comparison
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// of the written data with the read data
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reg [1:0] mst_exec_state;
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// AXI4LITE signals
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//AXI4 internal temp signals
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reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg axi_awvalid;
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reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
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reg axi_wlast;
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reg axi_wvalid;
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reg axi_bready;
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reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg axi_arvalid;
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reg axi_rready;
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//write beat count in a burst
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reg [C_TRANSACTIONS_NUM : 0] write_index;
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//read beat count in a burst
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reg [C_TRANSACTIONS_NUM : 0] read_index;
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//size of C_M_AXI_BURST_LEN length burst in bytes
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wire [C_TRANSACTIONS_NUM+2 : 0] burst_size_bytes;
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//The burst counters are used to track the number of burst transfers of C_M_AXI_BURST_LEN burst length needed to transfer 2^C_MASTER_LENGTH bytes of data.
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reg [C_NO_BURSTS_REQ : 0] write_burst_counter;
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reg [C_NO_BURSTS_REQ : 0] read_burst_counter;
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reg start_single_burst_write;
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reg start_single_burst_read;
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reg writes_done;
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reg reads_done;
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reg error_reg;
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reg compare_done;
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reg read_mismatch;
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reg burst_write_active;
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reg burst_read_active;
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reg [C_M_AXI_DATA_WIDTH-1 : 0] expected_rdata;
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//Interface response error flags
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wire write_resp_error;
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wire read_resp_error;
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wire wnext;
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wire rnext;
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reg init_txn_ff;
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reg init_txn_ff2;
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reg init_txn_edge;
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wire init_txn_pulse;
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// I/O Connections assignments
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//I/O Connections. Write Address (AW)
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assign M_AXI_AWID = 'b0;
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//The AXI address is a concatenation of the target base address + active offset range
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assign M_AXI_AWADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_awaddr;
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//Burst LENgth is number of transaction beats, minus 1
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assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1;
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//Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
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assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
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//INCR burst type is usually used, except for keyhole bursts
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assign M_AXI_AWBURST = 2'b01;
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assign M_AXI_AWLOCK = 1'b0;
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//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
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assign M_AXI_AWCACHE = 4'b0010;
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assign M_AXI_AWPROT = 3'h0;
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assign M_AXI_AWQOS = 4'h0;
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assign M_AXI_AWUSER = 'b1;
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assign M_AXI_AWVALID = axi_awvalid;
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//Write Data(W)
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assign M_AXI_WDATA = axi_wdata;
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//All bursts are complete and aligned in this example
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assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
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assign M_AXI_WLAST = axi_wlast;
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assign M_AXI_WUSER = 'b0;
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assign M_AXI_WVALID = axi_wvalid;
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//Write Response (B)
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assign M_AXI_BREADY = axi_bready;
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//Read Address (AR)
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assign M_AXI_ARID = 'b0;
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assign M_AXI_ARADDR = C_M_TARGET_SLAVE_BASE_ADDR + axi_araddr;
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//Burst LENgth is number of transaction beats, minus 1
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assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1;
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//Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
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assign M_AXI_ARSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1);
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//INCR burst type is usually used, except for keyhole bursts
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assign M_AXI_ARBURST = 2'b01;
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assign M_AXI_ARLOCK = 1'b0;
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//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
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assign M_AXI_ARCACHE = 4'b0010;
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assign M_AXI_ARPROT = 3'h0;
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assign M_AXI_ARQOS = 4'h0;
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assign M_AXI_ARUSER = 'b1;
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assign M_AXI_ARVALID = axi_arvalid;
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//Read and Read Response (R)
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assign M_AXI_RREADY = axi_rready;
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//Example design I/O
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assign TXN_DONE = compare_done;
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//Burst size in bytes
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assign burst_size_bytes = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH/8;
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assign init_txn_pulse = (!init_txn_ff2) && init_txn_ff;
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//Generate a pulse to initiate AXI transaction.
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always @(posedge M_AXI_ACLK)
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begin
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// Initiates AXI transaction delay
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if (M_AXI_ARESETN == 0 )
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begin
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init_txn_ff <= 1'b0;
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init_txn_ff2 <= 1'b0;
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end
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else
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begin
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init_txn_ff <= INIT_AXI_TXN;
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init_txn_ff2 <= init_txn_ff;
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end
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end
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//--------------------
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//Write Address Channel
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//--------------------
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// The purpose of the write address channel is to request the address and
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// command information for the entire transaction. It is a single beat
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// of information.
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// The AXI4 Write address channel in this example will continue to initiate
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// write commands as fast as it is allowed by the slave/interconnect.
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// The address will be incremented on each accepted address transaction,
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// by burst_size_byte to point to the next address.
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always @(posedge M_AXI_ACLK)
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begin
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if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
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begin
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axi_awvalid <= 1'b0;
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end
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// If previously not valid , start next transaction
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else if (~axi_awvalid && start_single_burst_write)
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begin
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axi_awvalid <= 1'b1;
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end
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/* Once asserted, VALIDs cannot be deasserted, so axi_awvalid
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must wait until transaction is accepted */
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else if (M_AXI_AWREADY && axi_awvalid)
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begin
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axi_awvalid <= 1'b0;
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end
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else
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axi_awvalid <= axi_awvalid;
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end
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// Next address after AWREADY indicates previous address acceptance
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always @(posedge M_AXI_ACLK)
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begin
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if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
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begin
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axi_awaddr <= 'b0;
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end
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else if (M_AXI_AWREADY && axi_awvalid)
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begin
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axi_awaddr <= axi_awaddr + burst_size_bytes;
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end
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else
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axi_awaddr <= axi_awaddr;
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end
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//--------------------
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//Write Data Channel
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//--------------------
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//The write data will continually try to push write data across the interface.
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//The amount of data accepted will depend on the AXI slave and the AXI
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//Interconnect settings, such as if there are FIFOs enabled in interconnect.
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//Note that there is no explicit timing relationship to the write address channel.
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//The write channel has its own throttling flag, separate from the AW channel.
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//Synchronization between the channels must be determined by the user.
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//The simpliest but lowest performance would be to only issue one address write
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//and write data burst at a time.
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//In this example they are kept in sync by using the same address increment
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//and burst sizes. Then the AW and W channels have their transactions measured
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//with threshold counters as part of the user logic, to make sure neither
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//channel gets too far ahead of each other.
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//Forward movement occurs when the write channel is valid and ready
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assign wnext = M_AXI_WREADY & axi_wvalid;
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// WVALID logic, similar to the axi_awvalid always block above
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always @(posedge M_AXI_ACLK)
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begin
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if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
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begin
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axi_wvalid <= 1'b0;
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end
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// If previously not valid, start next transaction
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else if (~axi_wvalid && start_single_burst_write)
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begin
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axi_wvalid <= 1'b1;
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end
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/* If WREADY and too many writes, throttle WVALID
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Once asserted, VALIDs cannot be deasserted, so WVALID
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must wait until burst is complete with WLAST */
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else if (wnext && axi_wlast)
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axi_wvalid <= 1'b0;
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else
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axi_wvalid <= axi_wvalid;
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end
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//WLAST generation on the MSB of a counter underflow
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// WVALID logic, similar to the axi_awvalid always block above
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always @(posedge M_AXI_ACLK)
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begin
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if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
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begin
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axi_wlast <= 1'b0;
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end
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// axi_wlast is asserted when the write index
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// count reaches the penultimate count to synchronize
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// with the last write data when write_index is b1111
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// else if (&(write_index[C_TRANSACTIONS_NUM-1:1])&& ~write_index[0] && wnext)
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else if (((write_index == C_M_AXI_BURST_LEN-2 && C_M_AXI_BURST_LEN >= 2) && wnext) || (C_M_AXI_BURST_LEN == 1 ))
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begin
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axi_wlast <= 1'b1;
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end
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// Deassrt axi_wlast when the last write data has been
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// accepted by the slave with a valid response
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else if (wnext)
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axi_wlast <= 1'b0;
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else if (axi_wlast && C_M_AXI_BURST_LEN == 1)
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axi_wlast <= 1'b0;
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else
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axi_wlast <= axi_wlast;
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end
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/* Burst length counter. Uses extra counter register bit to indicate terminal
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count to reduce decode logic */
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|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_write == 1'b1)
|
|
begin
|
|
write_index <= 0;
|
|
end
|
|
else if (wnext && (write_index != C_M_AXI_BURST_LEN-1))
|
|
begin
|
|
write_index <= write_index + 1;
|
|
end
|
|
else
|
|
write_index <= write_index;
|
|
end
|
|
|
|
|
|
/* Write Data Generator
|
|
Data pattern is only a simple incrementing count from 0 for each burst */
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
axi_wdata <= 'b1;
|
|
//else if (wnext && axi_wlast)
|
|
// axi_wdata <= 'b0;
|
|
else if (wnext)
|
|
axi_wdata <= axi_wdata + 1;
|
|
else
|
|
axi_wdata <= axi_wdata;
|
|
end
|
|
|
|
|
|
//----------------------------
|
|
//Write Response (B) Channel
|
|
//----------------------------
|
|
|
|
//The write response channel provides feedback that the write has committed
|
|
//to memory. BREADY will occur when all of the data and the write address
|
|
//has arrived and been accepted by the slave.
|
|
|
|
//The write issuance (number of outstanding write addresses) is started by
|
|
//the Address Write transfer, and is completed by a BREADY/BRESP.
|
|
|
|
//While negating BREADY will eventually throttle the AWREADY signal,
|
|
//it is best not to throttle the whole data channel this way.
|
|
|
|
//The BRESP bit [1] is used indicate any errors from the interconnect or
|
|
//slave for the entire write burst. This example will capture the error
|
|
//into the ERROR output.
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
|
|
begin
|
|
axi_bready <= 1'b0;
|
|
end
|
|
// accept/acknowledge bresp with axi_bready by the master
|
|
// when M_AXI_BVALID is asserted by slave
|
|
else if (M_AXI_BVALID && ~axi_bready)
|
|
begin
|
|
axi_bready <= 1'b1;
|
|
end
|
|
// deassert after one clock cycle
|
|
else if (axi_bready)
|
|
begin
|
|
axi_bready <= 1'b0;
|
|
end
|
|
// retain the previous value
|
|
else
|
|
axi_bready <= axi_bready;
|
|
end
|
|
|
|
|
|
//Flag any write response errors
|
|
assign write_resp_error = axi_bready & M_AXI_BVALID & M_AXI_BRESP[1];
|
|
|
|
|
|
//----------------------------
|
|
//Read Address Channel
|
|
//----------------------------
|
|
|
|
//The Read Address Channel (AW) provides a similar function to the
|
|
//Write Address channel- to provide the tranfer qualifiers for the burst.
|
|
|
|
//In this example, the read address increments in the same
|
|
//manner as the write address channel.
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
|
|
begin
|
|
axi_arvalid <= 1'b0;
|
|
end
|
|
// If previously not valid , start next transaction
|
|
else if (~axi_arvalid && start_single_burst_read)
|
|
begin
|
|
axi_arvalid <= 1'b1;
|
|
end
|
|
else if (M_AXI_ARREADY && axi_arvalid)
|
|
begin
|
|
axi_arvalid <= 1'b0;
|
|
end
|
|
else
|
|
axi_arvalid <= axi_arvalid;
|
|
end
|
|
|
|
|
|
// Next address after ARREADY indicates previous address acceptance
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
begin
|
|
axi_araddr <= 'b0;
|
|
end
|
|
else if (M_AXI_ARREADY && axi_arvalid)
|
|
begin
|
|
axi_araddr <= axi_araddr + burst_size_bytes;
|
|
end
|
|
else
|
|
axi_araddr <= axi_araddr;
|
|
end
|
|
|
|
|
|
//--------------------------------
|
|
//Read Data (and Response) Channel
|
|
//--------------------------------
|
|
|
|
// Forward movement occurs when the channel is valid and ready
|
|
assign rnext = M_AXI_RVALID && axi_rready;
|
|
|
|
|
|
// Burst length counter. Uses extra counter register bit to indicate
|
|
// terminal count to reduce decode logic
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 || start_single_burst_read)
|
|
begin
|
|
read_index <= 0;
|
|
end
|
|
else if (rnext && (read_index != C_M_AXI_BURST_LEN-1))
|
|
begin
|
|
read_index <= read_index + 1;
|
|
end
|
|
else
|
|
read_index <= read_index;
|
|
end
|
|
|
|
|
|
/*
|
|
The Read Data channel returns the results of the read request
|
|
|
|
In this example the data checker is always able to accept
|
|
more data, so no need to throttle the RREADY signal
|
|
*/
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
|
|
begin
|
|
axi_rready <= 1'b0;
|
|
end
|
|
// accept/acknowledge rdata/rresp with axi_rready by the master
|
|
// when M_AXI_RVALID is asserted by slave
|
|
else if (M_AXI_RVALID)
|
|
begin
|
|
if (M_AXI_RLAST && axi_rready)
|
|
begin
|
|
axi_rready <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
axi_rready <= 1'b1;
|
|
end
|
|
end
|
|
// retain the previous value
|
|
end
|
|
|
|
//Check received read data against data generator
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
begin
|
|
read_mismatch <= 1'b0;
|
|
end
|
|
//Only check data when RVALID is active
|
|
else if (rnext && (M_AXI_RDATA != expected_rdata))
|
|
begin
|
|
read_mismatch <= 1'b1;
|
|
end
|
|
else
|
|
read_mismatch <= 1'b0;
|
|
end
|
|
|
|
//Flag any read response errors
|
|
assign read_resp_error = axi_rready & M_AXI_RVALID & M_AXI_RRESP[1];
|
|
|
|
|
|
//----------------------------------------
|
|
//Example design read check data generator
|
|
//-----------------------------------------
|
|
|
|
//Generate expected read data to check against actual read data
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)// || M_AXI_RLAST)
|
|
expected_rdata <= 'b1;
|
|
else if (M_AXI_RVALID && axi_rready)
|
|
expected_rdata <= expected_rdata + 1;
|
|
else
|
|
expected_rdata <= expected_rdata;
|
|
end
|
|
|
|
|
|
//----------------------------------
|
|
//Example design error register
|
|
//----------------------------------
|
|
|
|
//Register and hold any data mismatches, or read/write interface errors
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
begin
|
|
error_reg <= 1'b0;
|
|
end
|
|
else if (read_mismatch || write_resp_error || read_resp_error)
|
|
begin
|
|
error_reg <= 1'b1;
|
|
end
|
|
else
|
|
error_reg <= error_reg;
|
|
end
|
|
|
|
|
|
//--------------------------------
|
|
//Example design throttling
|
|
//--------------------------------
|
|
|
|
// For maximum port throughput, this user example code will try to allow
|
|
// each channel to run as independently and as quickly as possible.
|
|
|
|
// However, there are times when the flow of data needs to be throtted by
|
|
// the user application. This example application requires that data is
|
|
// not read before it is written and that the write channels do not
|
|
// advance beyond an arbitrary threshold (say to prevent an
|
|
// overrun of the current read address by the write address).
|
|
|
|
// From AXI4 Specification, 13.13.1: "If a master requires ordering between
|
|
// read and write transactions, it must ensure that a response is received
|
|
// for the previous transaction before issuing the next transaction."
|
|
|
|
// This example accomplishes this user application throttling through:
|
|
// -Reads wait for writes to fully complete
|
|
// -Address writes wait when not read + issued transaction counts pass
|
|
// a parameterized threshold
|
|
// -Writes wait when a not read + active data burst count pass
|
|
// a parameterized threshold
|
|
|
|
// write_burst_counter counter keeps track with the number of burst transaction initiated
|
|
// against the number of burst transactions the master needs to initiate
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
|
|
begin
|
|
write_burst_counter <= 'b0;
|
|
end
|
|
else if (M_AXI_AWREADY && axi_awvalid)
|
|
begin
|
|
if (write_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
|
|
begin
|
|
write_burst_counter <= write_burst_counter + 1'b1;
|
|
//write_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
|
|
end
|
|
end
|
|
else
|
|
write_burst_counter <= write_burst_counter;
|
|
end
|
|
|
|
// read_burst_counter counter keeps track with the number of burst transaction initiated
|
|
// against the number of burst transactions the master needs to initiate
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
begin
|
|
read_burst_counter <= 'b0;
|
|
end
|
|
else if (M_AXI_ARREADY && axi_arvalid)
|
|
begin
|
|
if (read_burst_counter[C_NO_BURSTS_REQ] == 1'b0)
|
|
begin
|
|
read_burst_counter <= read_burst_counter + 1'b1;
|
|
//read_burst_counter[C_NO_BURSTS_REQ] <= 1'b1;
|
|
end
|
|
end
|
|
else
|
|
read_burst_counter <= read_burst_counter;
|
|
end
|
|
|
|
|
|
//implement master command interface state machine
|
|
|
|
always @ ( posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 1'b0 )
|
|
begin
|
|
// reset condition
|
|
// All the signals are assigned default values under reset condition
|
|
mst_exec_state <= IDLE;
|
|
start_single_burst_write <= 1'b0;
|
|
start_single_burst_read <= 1'b0;
|
|
compare_done <= 1'b0;
|
|
ERROR <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
|
|
// state transition
|
|
case (mst_exec_state)
|
|
|
|
IDLE:
|
|
// This state is responsible to wait for user defined C_M_START_COUNT
|
|
// number of clock cycles.
|
|
if ( init_txn_pulse == 1'b1)
|
|
begin
|
|
mst_exec_state <= INIT_WRITE;
|
|
ERROR <= 1'b0;
|
|
compare_done <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
mst_exec_state <= IDLE;
|
|
end
|
|
|
|
INIT_WRITE:
|
|
// This state is responsible to issue start_single_write pulse to
|
|
// initiate a write transaction. Write transactions will be
|
|
// issued until burst_write_active signal is asserted.
|
|
// write controller
|
|
if (writes_done)
|
|
begin
|
|
mst_exec_state <= INIT_READ;//
|
|
end
|
|
else
|
|
begin
|
|
mst_exec_state <= INIT_WRITE;
|
|
|
|
if (~axi_awvalid && ~start_single_burst_write && ~burst_write_active)
|
|
begin
|
|
start_single_burst_write <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
start_single_burst_write <= 1'b0; //Negate to generate a pulse
|
|
end
|
|
end
|
|
|
|
INIT_READ:
|
|
// This state is responsible to issue start_single_read pulse to
|
|
// initiate a read transaction. Read transactions will be
|
|
// issued until burst_read_active signal is asserted.
|
|
// read controller
|
|
if (reads_done)
|
|
begin
|
|
mst_exec_state <= INIT_COMPARE;
|
|
end
|
|
else
|
|
begin
|
|
mst_exec_state <= INIT_READ;
|
|
|
|
if (~axi_arvalid && ~burst_read_active && ~start_single_burst_read)
|
|
begin
|
|
start_single_burst_read <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
start_single_burst_read <= 1'b0; //Negate to generate a pulse
|
|
end
|
|
end
|
|
|
|
INIT_COMPARE:
|
|
// This state is responsible to issue the state of comparison
|
|
// of written data with the read data. If no error flags are set,
|
|
// compare_done signal will be asseted to indicate success.
|
|
//if (~error_reg)
|
|
begin
|
|
ERROR <= error_reg;
|
|
mst_exec_state <= IDLE;
|
|
compare_done <= 1'b1;
|
|
end
|
|
default :
|
|
begin
|
|
mst_exec_state <= IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end //MASTER_EXECUTION_PROC
|
|
|
|
|
|
// burst_write_active signal is asserted when there is a burst write transaction
|
|
// is initiated by the assertion of start_single_burst_write. burst_write_active
|
|
// signal remains asserted until the burst write is accepted by the slave
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
burst_write_active <= 1'b0;
|
|
|
|
//The burst_write_active is asserted when a write burst transaction is initiated
|
|
else if (start_single_burst_write)
|
|
burst_write_active <= 1'b1;
|
|
else if (M_AXI_BVALID && axi_bready)
|
|
burst_write_active <= 0;
|
|
end
|
|
|
|
// Check for last write completion.
|
|
|
|
// This logic is to qualify the last write count with the final write
|
|
// response. This demonstrates how to confirm that a write has been
|
|
// committed.
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
writes_done <= 1'b0;
|
|
|
|
//The writes_done should be associated with a bready response
|
|
//else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
|
|
else if (M_AXI_BVALID && (write_burst_counter[C_NO_BURSTS_REQ]) && axi_bready)
|
|
writes_done <= 1'b1;
|
|
else
|
|
writes_done <= writes_done;
|
|
end
|
|
|
|
// burst_read_active signal is asserted when there is a burst write transaction
|
|
// is initiated by the assertion of start_single_burst_write. start_single_burst_read
|
|
// signal remains asserted until the burst read is accepted by the master
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
burst_read_active <= 1'b0;
|
|
|
|
//The burst_write_active is asserted when a write burst transaction is initiated
|
|
else if (start_single_burst_read)
|
|
burst_read_active <= 1'b1;
|
|
else if (M_AXI_RVALID && axi_rready && M_AXI_RLAST)
|
|
burst_read_active <= 0;
|
|
end
|
|
|
|
|
|
// Check for last read completion.
|
|
|
|
// This logic is to qualify the last read count with the final read
|
|
// response. This demonstrates how to confirm that a read has been
|
|
// committed.
|
|
|
|
always @(posedge M_AXI_ACLK)
|
|
begin
|
|
if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1)
|
|
reads_done <= 1'b0;
|
|
|
|
//The reads_done should be associated with a rready response
|
|
//else if (M_AXI_BVALID && axi_bready && (write_burst_counter == {(C_NO_BURSTS_REQ-1){1}}) && axi_wlast)
|
|
else if (M_AXI_RVALID && axi_rready && (read_index == C_M_AXI_BURST_LEN-1) && (read_burst_counter[C_NO_BURSTS_REQ]))
|
|
reads_done <= 1'b1;
|
|
else
|
|
reads_done <= reads_done;
|
|
end
|
|
|
|
// Add user logic here
|
|
|
|
// User logic ends
|
|
|
|
endmodule
|