user.org user ledmatrix_v1_0 1.0 m00_axi AWID m00_axi_awid AWADDR m00_axi_awaddr AWLEN m00_axi_awlen AWSIZE m00_axi_awsize AWBURST m00_axi_awburst AWLOCK m00_axi_awlock AWCACHE m00_axi_awcache AWPROT m00_axi_awprot AWQOS m00_axi_awqos AWUSER m00_axi_awuser AWVALID m00_axi_awvalid AWREADY m00_axi_awready WDATA m00_axi_wdata WSTRB m00_axi_wstrb WLAST m00_axi_wlast WUSER m00_axi_wuser WVALID m00_axi_wvalid WREADY m00_axi_wready BID m00_axi_bid BRESP m00_axi_bresp BUSER m00_axi_buser BVALID m00_axi_bvalid BREADY m00_axi_bready ARID m00_axi_arid ARADDR m00_axi_araddr ARLEN m00_axi_arlen ARSIZE m00_axi_arsize ARBURST m00_axi_arburst ARLOCK m00_axi_arlock ARCACHE m00_axi_arcache ARPROT m00_axi_arprot ARQOS m00_axi_arqos ARUSER m00_axi_aruser ARVALID m00_axi_arvalid ARREADY m00_axi_arready RID m00_axi_rid RDATA m00_axi_rdata RRESP m00_axi_rresp RLAST m00_axi_rlast RUSER m00_axi_ruser RVALID m00_axi_rvalid RREADY m00_axi_rready s00_axi AWADDR s00_axi_awaddr AWPROT s00_axi_awprot AWVALID s00_axi_awvalid AWREADY s00_axi_awready WDATA s00_axi_wdata WSTRB s00_axi_wstrb WVALID s00_axi_wvalid WREADY s00_axi_wready BRESP s00_axi_bresp BVALID s00_axi_bvalid BREADY s00_axi_bready ARADDR s00_axi_araddr ARPROT s00_axi_arprot ARVALID s00_axi_arvalid ARREADY s00_axi_arready RDATA s00_axi_rdata RRESP s00_axi_rresp RVALID s00_axi_rvalid RREADY s00_axi_rready m00_axi_aresetn RST m00_axi_aresetn POLARITY ACTIVE_LOW s00_axi_aresetn RST s00_axi_aresetn POLARITY ACTIVE_LOW m00_axi_aclk CLK m00_axi_aclk ASSOCIATED_BUSIF m00_axi ASSOCIATED_RESET m00_axi_aresetn s00_axi_aclk CLK s00_axi_aclk ASSOCIATED_BUSIF s00_axi ASSOCIATED_RESET s00_axi_aresetn led_clk CLK led_clk m00_axi 4294967296 32 s00_axi reg0 0 32 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog ledmatrix_v1_0 xilinx_anylanguagesynthesis_view_fileset viewChecksum 8d842412 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog ledmatrix_v1_0 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 8d842412 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 4635262c led_r0 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_r1 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_g0 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_g1 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_b0 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_b1 out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_bank out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_clk out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_stb out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation led_oe out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sys_rst in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_awaddr in 4 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_awprot in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_awvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_awready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_wdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_wstrb in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_wvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_wready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_bresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_bvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_bready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_araddr in 4 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_arprot in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_arvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s00_axi_arready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_rdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_rresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_rvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s00_axi_rready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_init_axi_txn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_txn_done out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_error out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_aclk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_aresetn in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awid out 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awaddr out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awuser out 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_awready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_wdata out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_wstrb out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_wlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_wuser out 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_wvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_wready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_bid in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_bresp in 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_buser in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_bvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_bready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arid out 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_araddr out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arlen out 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arsize out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arburst out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arlock out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arcache out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arprot out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arqos out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_aruser out 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m00_axi_arready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rid in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rdata in 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rresp in 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rlast in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_ruser in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m00_axi_rready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation C_S00_AXI_DATA_WIDTH C S00 Axi Data Width 32 C_S00_AXI_ADDR_WIDTH C S00 Axi Addr Width 5 C_M00_AXI_TARGET_SLAVE_BASE_ADDR C M00 Axi Target Slave Base Addr 0x40000000 C_M00_AXI_BURST_LEN C M00 Axi Burst Len 16 C_M00_AXI_ID_WIDTH C M00 Axi Id Width 1 C_M00_AXI_ADDR_WIDTH C M00 Axi Addr Width 32 C_M00_AXI_DATA_WIDTH C M00 Axi Data Width 32 C_M00_AXI_AWUSER_WIDTH C M00 Axi Awuser Width 0 C_M00_AXI_ARUSER_WIDTH C M00 Axi Aruser Width 0 C_M00_AXI_WUSER_WIDTH C M00 Axi Wuser Width 0 C_M00_AXI_RUSER_WIDTH C M00 Axi Ruser Width 0 C_M00_AXI_BUSER_WIDTH C M00 Axi Buser Width 0 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset hdl/ledmatrix_v1_0_S00_AXI.v verilogSource hdl/ledmatrix_v1_0_M00_AXI.v verilogSource src/blitter.v verilogSource hdl/ledmatrix_v1_0.v verilogSource CHECKSUM_a4469612 xilinx_anylanguagebehavioralsimulation_view_fileset hdl/ledmatrix_v1_0_S00_AXI.v verilogSource USED_IN_ipstatic hdl/ledmatrix_v1_0_M00_AXI.v verilogSource USED_IN_ipstatic src/blitter.v verilogSource USED_IN_ipstatic hdl/ledmatrix_v1_0.v verilogSource USED_IN_ipstatic xilinx_xpgui_view_fileset xgui/ledmatrix_v1_0_v1_0.tcl tclSource CHECKSUM_4635262c XGUI_VERSION_2 ledmatrix_v1_0_v1_0 C_S00_AXI_DATA_WIDTH C S00 Axi Data Width 32 C_S00_AXI_ADDR_WIDTH C S00 Axi Addr Width 5 C_M00_AXI_TARGET_SLAVE_BASE_ADDR C M00 Axi Target Slave Base Addr 0x40000000 C_M00_AXI_BURST_LEN C M00 Axi Burst Len 16 C_M00_AXI_ID_WIDTH C M00 Axi Id Width 1 C_M00_AXI_ADDR_WIDTH C M00 Axi Addr Width 32 C_M00_AXI_DATA_WIDTH C M00 Axi Data Width 32 C_M00_AXI_AWUSER_WIDTH C M00 Axi Awuser Width 0 C_M00_AXI_ARUSER_WIDTH C M00 Axi Aruser Width 0 C_M00_AXI_WUSER_WIDTH C M00 Axi Wuser Width 0 C_M00_AXI_RUSER_WIDTH C M00 Axi Ruser Width 0 C_M00_AXI_BUSER_WIDTH C M00 Axi Buser Width 0 Component_Name ledmatrix_v1_0_v1_0 zynq /UserIP ledmatrix_v1_0_v1_0 12 2015-11-18T08:12:28Z /home/q3k/ip_repo/ledmatrix_1.0 2015.3