148 lines
3.1 KiB
Verilog
148 lines
3.1 KiB
Verilog
// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Released under the 2-clause BSD license - see the COPYING file
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`timescale 1ns / 1ps
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module top(
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// Board-specific signals
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input sys_clk,
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input sys_rst,
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// To EC
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input [7:0] data,
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output reg [14:0] address,
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output reg oe,
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output reg ce,
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output xout,
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// UART signals for control
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output uart_signal_tx,
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input uart_signal_rx,
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// Debug signals
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output led0,
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output debug
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);
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// FSM states
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`define STATE_IDLE 4'b0000
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`define STATE_ASSERT_ADDRESS 4'b0001
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`define STATE_READ_DATA 4'b0010
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`define STATE_OUTPUT 4'b0011
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`define STATE_OUTPUT_WAIT 4'b0100
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// State of our FSM
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reg [3:0] state;
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assign led0 = state != 0;
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// Clocks 'n stuff
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// 'Main' clock
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reg [11:0] clock_counter;
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wire clock = clock_counter[11];
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// UART clock
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reg [7:0] uart_clock_counter;
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reg uart_clock;
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assign debug = uart_clock;
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// EC clock
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reg [2:0] ec_clock_counter;
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reg ec_clock;
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assign xout = ec_clock;
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// UART
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reg uart_latch;
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wire uart_receied;
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reg uart_received_clear;
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wire [7:0] uart_rx;
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wire uart_transmitted;
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uart_controller uart(
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.tx_data_in(data),
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.tx_data_latch(uart_latch),
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.clock(uart_clock),
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.reset(!sys_rst),
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.tx_transmitted(uart_transmitted),
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.tx_signal(uart_signal_tx),
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.rx_present(uart_received),
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.rx_present_clear(uart_received_clear),
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.rx_data(uart_rx),
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.rx_signal(uart_signal_rx));
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// Internal reader registers
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reg [14:0] read_address;
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reg [8:0] bytes_left;
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// Clocks
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always @(posedge sys_clk) begin
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clock_counter <= clock_counter + 1;
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if (uart_clock_counter >= 216) begin
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uart_clock <= !uart_clock;
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uart_clock_counter <= 0;
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end else begin
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uart_clock_counter <= uart_clock_counter + 1;
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end
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if (ec_clock_counter >= 4) begin
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ec_clock <= !ec_clock;
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ec_clock_counter <= 0;
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end else begin
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ec_clock_counter <= ec_clock_counter + 1;
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end
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//clock_counter <= 0;
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//uart_clock_counter <= 0;
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//uart_clock <= 0;
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//ec_clock_counter <= 0;
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//ec_clock <= 0;
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end
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// State machine
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always @(posedge clock) begin
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if (!sys_rst) begin
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// reset condition
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state <= `STATE_IDLE;
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uart_received_clear <= 0;
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uart_latch <= 0;
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read_address <= 0;
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oe <= 1;
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ce <= 1;
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end else begin
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case (state)
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`STATE_IDLE: begin
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if (uart_received) begin
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uart_received_clear <= 1;
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read_address <= (uart_rx * 256) & 15'h7FFF;
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state <= `STATE_ASSERT_ADDRESS;
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bytes_left <= 9'h100;
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end
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end
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`STATE_ASSERT_ADDRESS: begin
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oe <= 0;
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ce <= 0;
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address <= read_address;
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state <= `STATE_READ_DATA;
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end
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`STATE_READ_DATA: begin
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state <= `STATE_OUTPUT;
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end
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`STATE_OUTPUT: begin
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if (uart_transmitted) begin
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uart_latch <= 1;
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state <= `STATE_OUTPUT_WAIT;
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end
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end
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`STATE_OUTPUT_WAIT: begin
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if (!uart_transmitted) begin
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bytes_left <= bytes_left - 1;
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read_address <= read_address + 1;
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uart_latch <= 0;
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if (bytes_left - 1 == 0) begin
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uart_received_clear <= 0;
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state <= `STATE_IDLE;
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end else begin
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state <= `STATE_ASSERT_ADDRESS;
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end
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end
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end
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endcase
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end
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end
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endmodule
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