diff options
| -rw-r--r-- | .gitignore | 61 | ||||
| -rw-r--r-- | ec-prom-dump.xise | 368 | ||||
| -rw-r--r-- | top.ucf | 35 | ||||
| -rw-r--r-- | top.v | 147 | ||||
| -rw-r--r-- | uart.v | 170 |
5 files changed, 781 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a93d456 --- /dev/null +++ b/.gitignore @@ -0,0 +1,61 @@ +# Created by https://www.gitignore.io + +### XilinxISE ### +# intermediate build files +*.bgn +*.bit +*.bld +*.cmd_log +*.drc +*.ll +*.lso +*.msd +*.msk +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*.par +*.pcf +*.prj +*.ptwx +*.rbb +*.rbd +*.stx +*.syr +*.twr +*.twx +*.unroutes +*.ut +*.xpi +*.xst +*_bitgen.xwbt +*_envsettings.html +*_map.map +*_map.mrp +*_map.ngm +*_map.xrpt +*_ngdbuild.xrpt +*_pad.csv +*_pad.txt +*_par.xrpt +*_summary.html +*_summary.xml +*_usage.xml +*_xst.xrpt + +# project-wide generated files +*.gise +par_usage_statistics.html +usage_statistics_webtalk.html +webtalk.log +webtalk_pn.xml + +# generated folders +iseconfig/ +xlnx_auto_0_xdb/ +xst/ +_ngo/ +_xmsgs/ + diff --git a/ec-prom-dump.xise b/ec-prom-dump.xise new file mode 100644 index 0000000..cff5cbc --- /dev/null +++ b/ec-prom-dump.xise @@ -0,0 +1,368 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> + + <header> + <!-- ISE source project file created by Project Navigator. --> + <!-- --> + <!-- This file contains project source information including a list of --> + <!-- project source files, project and process properties. This file, --> + <!-- along with the project source files, is sufficient to open and --> + <!-- implement in ISE Project Navigator. --> + <!-- --> + <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> + </header> + + <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/> + + <files> + <file xil_pn:name="top.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + </file> + <file xil_pn:name="uart.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + </file> + <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> + </files> + + <properties> + <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> + <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> + <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> + <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> + <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> + <property xil_pn:name="Configuration Pin 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xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> + <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> + <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/> + <property xil_pn:name="Device Family" xil_pn:value="Spartan6" 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xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="ec-prom-dump" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-15T18:53:09" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2C461296A6AEC0F3354D5114A64A9BAC" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> @@ -0,0 +1,35 @@ + +# PlanAhead Generated physical constraints + +NET "address[0]" LOC = P123; +NET "address[1]" LOC = P121; +NET "address[2]" LOC = P120; +NET "address[3]" LOC = P119; +NET "address[4]" LOC = P118; +NET "address[5]" LOC = P117; +NET "address[6]" LOC = P116; +NET "address[7]" LOC = P115; +NET "address[8]" LOC = P114; +NET "address[9]" LOC = P112; +NET "address[10]" LOC = P111; +NET "address[11]" LOC = P105; +NET "address[12]" LOC = P104; +NET "address[13]" LOC = P102; +NET "address[14]" LOC = P101; +NET "data[0]" LOC = P80; +NET "data[1]" LOC = P79; +NET "data[2]" LOC = P78; +NET "data[3]" LOC = P75; +NET "data[4]" LOC = P74; +NET "data[5]" LOC = P67; +NET "data[6]" LOC = P66; +NET "data[7]" LOC = P59; +NET "oe" LOC = P87; +NET "ce" LOC = P85; +NET "uart_signal_tx" LOC = P83; +NET "uart_signal_rx" LOC = P84; +NET "xout" LOC = P82; +NET "sys_clk" LOC = P55; +NET "sys_rst" LOC = P124; +NET "led0" LOC = P127; +NET "debug" LOC = P97;
\ No newline at end of file @@ -0,0 +1,147 @@ +// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl> +// Released under the 2-clause BSD license - see the COPYING file + +`timescale 1ns / 1ps + +module top( + // Board-specific signals + input sys_clk, + input sys_rst, + + // To EC + input [7:0] data, + output reg [14:0] address, + output reg oe, + output reg ce, + output xout, + + // UART signals for control + output uart_signal_tx, + input uart_signal_rx, + + // Debug signals + output led0, + output debug + ); + +// FSM states +`define STATE_IDLE 4'b0000 +`define STATE_ASSERT_ADDRESS 4'b0001 +`define STATE_READ_DATA 4'b0010 +`define STATE_OUTPUT 4'b0011 +`define STATE_OUTPUT_WAIT 4'b0100 +// State of our FSM +reg [3:0] state; +assign led0 = state != 0; + +// Clocks 'n stuff +// 'Main' clock +reg [11:0] clock_counter; +wire clock = clock_counter[11]; +// UART clock +reg [7:0] uart_clock_counter; +reg uart_clock; +assign debug = uart_clock; +// EC clock +reg [2:0] ec_clock_counter; +reg ec_clock; +assign xout = ec_clock; + +// UART +reg uart_latch; +wire uart_receied; +reg uart_received_clear; +wire [7:0] uart_rx; +wire uart_transmitted; +uart_controller uart( + .tx_data_in(data), + .tx_data_latch(uart_latch), + .clock(uart_clock), + .reset(!sys_rst), + .tx_transmitted(uart_transmitted), + .tx_signal(uart_signal_tx), + .rx_present(uart_received), + .rx_present_clear(uart_received_clear), + .rx_data(uart_rx), + .rx_signal(uart_signal_rx)); + +// Internal reader registers +reg [14:0] read_address; +reg [8:0] bytes_left; + +// Clocks +always @(posedge sys_clk) begin + clock_counter <= clock_counter + 1; + if (uart_clock_counter >= 216) begin + uart_clock <= !uart_clock; + uart_clock_counter <= 0; + end else begin + uart_clock_counter <= uart_clock_counter + 1; + end + if (ec_clock_counter >= 4) begin + ec_clock <= !ec_clock; + ec_clock_counter <= 0; + end else begin + ec_clock_counter <= ec_clock_counter + 1; + end + + //clock_counter <= 0; + //uart_clock_counter <= 0; + //uart_clock <= 0; + //ec_clock_counter <= 0; + //ec_clock <= 0; +end + +// State machine +always @(posedge clock) begin + if (!sys_rst) begin + // reset condition + state <= `STATE_IDLE; + uart_received_clear <= 0; + uart_latch <= 0; + read_address <= 0; + oe <= 1; + ce <= 1; + end else begin + case (state) + `STATE_IDLE: begin + if (uart_received) begin + uart_received_clear <= 1; + read_address <= (uart_rx * 256) & 15'h7FFF; + state <= `STATE_ASSERT_ADDRESS; + bytes_left <= 9'h100; + end + end + `STATE_ASSERT_ADDRESS: begin + oe <= 0; + ce <= 0; + address <= read_address; + state <= `STATE_READ_DATA; + end + `STATE_READ_DATA: begin + state <= `STATE_OUTPUT; + end + `STATE_OUTPUT: begin + if (uart_transmitted) begin + uart_latch <= 1; + state <= `STATE_OUTPUT_WAIT; + end + end + `STATE_OUTPUT_WAIT: begin + if (!uart_transmitted) begin + bytes_left <= bytes_left - 1; + read_address <= read_address + 1; + uart_latch <= 0; + if (bytes_left - 1 == 0) begin + uart_received_clear <= 0; + state <= `STATE_IDLE; + end else begin + state <= `STATE_ASSERT_ADDRESS; + end + end + end + endcase + end +end + +endmodule @@ -0,0 +1,170 @@ +// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl> +// Released under the 2-clause BSD license - see the COPYING file + +`timescale 1ns / 1ps + +/// This is not the prettiest UART you've seen... + +module uart_controller( + // Data input + input [7:0] tx_data_in, + // Data input latch + input tx_data_latch, + + // baud rate clock + input clock, + + // reset line + input reset, + + // goes 1 when the UART finished transmitting + output reg tx_transmitted, + // the actual UART transmitter output + output reg tx_signal, + + output reg rx_present, + input rx_present_clear, + output reg [7:0] rx_data, + + input rx_signal + ); + + // Internal TX data (latched from tx_data_in) + reg [7:0] tx_data; + + reg [3:0] tx_state; + reg [3:0] rx_state; + `define IDLE 0 + `define START 1 + `define BIT0 2 + `define BIT1 3 + `define BIT2 4 + `define BIT3 5 + `define BIT4 6 + `define BIT5 7 + `define BIT6 8 + `define BIT7 9 + `define STOP 10 + + /// Receiver + always @(posedge clock) + begin + if (reset) begin + rx_state <= `IDLE; + rx_present <= 0; + rx_data <= 0; + end else begin + if (rx_present_clear) + rx_present <= 0; + case (rx_state) + `IDLE: begin + if (!rx_signal) begin + // We received a start bit + rx_state <= `BIT0; + rx_present <= 0; + end + end + `BIT0: begin + rx_data[0] <= rx_signal; + rx_state <= `BIT1; + end + `BIT1: begin + rx_data[1] <= rx_signal; + rx_state <= `BIT2; + end + `BIT2: begin + rx_data[2] <= rx_signal; + rx_state <= `BIT3; + end + `BIT3: begin + rx_data[3] <= rx_signal; + rx_state <= `BIT4; + end + `BIT4: begin + rx_data[4] <= rx_signal; + rx_state <= `BIT5; + end + `BIT5: begin + rx_data[5] <= rx_signal; + rx_state <= `BIT6; + end + `BIT6: begin + rx_data[6] <= rx_signal; + rx_state <= `BIT7; + end + `BIT7: begin + rx_data[7] <= rx_signal; + rx_state <= `STOP; + end + `STOP: begin + rx_present <= 1; + rx_state <= `IDLE; + end + endcase + end + end + + /// Transmitter + always @(posedge clock) + begin + if (reset) begin + tx_state <= `IDLE; + tx_signal <= 1; + tx_data <= 0; + tx_transmitted <= 1; + end else begin + case (tx_state) + `IDLE: begin + if (tx_data_latch) + begin + tx_data <= tx_data_in; + tx_state <= `START; + tx_transmitted <= 0; + end + end + `START: begin + tx_signal <= 0; + tx_state <= `BIT0; + end + `BIT0: begin + tx_signal <= tx_data[0]; + tx_state <= `BIT1; + end + `BIT1: begin + tx_signal <= tx_data[1]; + tx_state <= `BIT2; + end + `BIT2: begin + tx_signal <= tx_data[2]; + tx_state <= `BIT3; + end + `BIT3: begin + tx_signal <= tx_data[3]; + tx_state <= `BIT4; + end + `BIT4: begin + tx_signal <= tx_data[4]; + tx_state <= `BIT5; + end + `BIT5: begin + tx_signal <= tx_data[5]; + tx_state <= `BIT6; + end + `BIT6: begin + tx_signal <= tx_data[6]; + tx_state <= `BIT7; + end + `BIT7: begin + tx_signal <= tx_data[7]; + tx_state <= `STOP; + end + `STOP: begin + tx_signal <= 1; + tx_state <= `IDLE; + tx_transmitted <= 1; + end + endcase + end + end + +endmodule |