171 lines
3.1 KiB
Verilog
171 lines
3.1 KiB
Verilog
// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Released under the 2-clause BSD license - see the COPYING file
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`timescale 1ns / 1ps
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/// This is not the prettiest UART you've seen...
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module uart_controller(
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// Data input
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input [7:0] tx_data_in,
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// Data input latch
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input tx_data_latch,
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// baud rate clock
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input clock,
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// reset line
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input reset,
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// goes 1 when the UART finished transmitting
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output reg tx_transmitted,
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// the actual UART transmitter output
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output reg tx_signal,
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output reg rx_present,
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input rx_present_clear,
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output reg [7:0] rx_data,
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input rx_signal
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);
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// Internal TX data (latched from tx_data_in)
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reg [7:0] tx_data;
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reg [3:0] tx_state;
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reg [3:0] rx_state;
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`define IDLE 0
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`define START 1
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`define BIT0 2
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`define BIT1 3
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`define BIT2 4
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`define BIT3 5
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`define BIT4 6
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`define BIT5 7
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`define BIT6 8
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`define BIT7 9
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`define STOP 10
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/// Receiver
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always @(posedge clock)
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begin
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if (reset) begin
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rx_state <= `IDLE;
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rx_present <= 0;
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rx_data <= 0;
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end else begin
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if (rx_present_clear)
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rx_present <= 0;
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case (rx_state)
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`IDLE: begin
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if (!rx_signal) begin
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// We received a start bit
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rx_state <= `BIT0;
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rx_present <= 0;
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end
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end
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`BIT0: begin
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rx_data[0] <= rx_signal;
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rx_state <= `BIT1;
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end
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`BIT1: begin
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rx_data[1] <= rx_signal;
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rx_state <= `BIT2;
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end
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`BIT2: begin
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rx_data[2] <= rx_signal;
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rx_state <= `BIT3;
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end
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`BIT3: begin
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rx_data[3] <= rx_signal;
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rx_state <= `BIT4;
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end
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`BIT4: begin
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rx_data[4] <= rx_signal;
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rx_state <= `BIT5;
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end
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`BIT5: begin
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rx_data[5] <= rx_signal;
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rx_state <= `BIT6;
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end
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`BIT6: begin
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rx_data[6] <= rx_signal;
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rx_state <= `BIT7;
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end
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`BIT7: begin
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rx_data[7] <= rx_signal;
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rx_state <= `STOP;
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end
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`STOP: begin
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rx_present <= 1;
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rx_state <= `IDLE;
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end
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endcase
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end
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end
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/// Transmitter
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always @(posedge clock)
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begin
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if (reset) begin
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tx_state <= `IDLE;
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tx_signal <= 1;
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tx_data <= 0;
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tx_transmitted <= 1;
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end else begin
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case (tx_state)
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`IDLE: begin
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if (tx_data_latch)
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begin
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tx_data <= tx_data_in;
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tx_state <= `START;
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tx_transmitted <= 0;
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end
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end
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`START: begin
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tx_signal <= 0;
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tx_state <= `BIT0;
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end
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`BIT0: begin
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tx_signal <= tx_data[0];
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tx_state <= `BIT1;
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end
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`BIT1: begin
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tx_signal <= tx_data[1];
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tx_state <= `BIT2;
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end
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`BIT2: begin
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tx_signal <= tx_data[2];
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tx_state <= `BIT3;
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end
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`BIT3: begin
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tx_signal <= tx_data[3];
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tx_state <= `BIT4;
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end
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`BIT4: begin
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tx_signal <= tx_data[4];
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tx_state <= `BIT5;
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end
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`BIT5: begin
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tx_signal <= tx_data[5];
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tx_state <= `BIT6;
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end
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`BIT6: begin
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tx_signal <= tx_data[6];
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tx_state <= `BIT7;
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end
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`BIT7: begin
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tx_signal <= tx_data[7];
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tx_state <= `STOP;
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end
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`STOP: begin
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tx_signal <= 1;
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tx_state <= `IDLE;
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tx_transmitted <= 1;
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end
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endcase
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end
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end
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endmodule
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