68 lines
1.6 KiB
Verilog
68 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@bazanski.pl>
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// Released under the 2-clause BSD license - see the COPYING file
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module sevenseg(
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// Value to be displayed (0-FFFF)
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input [15:0] value,
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output reg [6:0] segments,
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output reg [3:0] anodes,
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input sys_clock,
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input reset
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);
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reg [1:0] current_anode;
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wire [3:0] current_digit[0:3];
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assign current_digit[0] = value[3:0];
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assign current_digit[1] = value[7:4];
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assign current_digit[2] = value[11:8];
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assign current_digit[3] = value[15:12];
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reg [10:0] clock_counter;
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reg clock;
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always @(posedge sys_clock)
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begin
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if (clock_counter >= 1024)
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begin
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clock_counter <= 0;
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clock <= !clock;
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end else begin
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clock_counter <= clock_counter + 1;
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end
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end
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always @(posedge clock)
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begin
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if (reset) begin
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segments <= 0;
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anodes <= 0;
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current_anode <= 0;
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end else begin
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current_anode <= current_anode + 1;
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anodes <= ~(1 << (3-current_anode));
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case (current_digit[current_anode])
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4'h0: segments <= 7'b1000000;
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4'h1: segments <= 7'b1111001;
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4'h2: segments <= 7'b0100100;
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4'h3: segments <= 7'b0110000;
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4'h4: segments <= 7'b0011001;
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4'h5: segments <= 7'b0010010;
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4'h6: segments <= 7'b0000010;
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4'h7: segments <= 7'b1111000;
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4'h8: segments <= 7'b0000000;
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4'h9: segments <= 7'b0011000;
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4'hA: segments <= 7'b0001000;
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4'hB: segments <= 7'b0000011;
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4'hC: segments <= 7'b1000110;
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4'hD: segments <= 7'b0100001;
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4'hE: segments <= 7'b0000110;
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4'hF: segments <= 7'b0001110;
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default: segments <= 7'b0110110;
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endcase
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end
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end
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endmodule
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