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authorSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 19:28:23 +0100
committerSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 19:28:23 +0100
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First commit, basic dumper
Diffstat (limited to 'uart.v')
-rw-r--r--uart.v104
1 files changed, 104 insertions, 0 deletions
diff --git a/uart.v b/uart.v
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+++ b/uart.v
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+// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@baznaski.pl>
+// Released under the 2-clause BSD license - see the COPYING file
+
+`timescale 1ns / 1ps
+
+/// This is not the prettiest UART you've seen...
+
+module uart_controller(
+ // Data input
+ input [7:0] tx_data_in,
+ // Data input latch
+ input tx_data_latch,
+
+ // baud rate clock
+ input tx_clock,
+
+ // reset line
+ input reset,
+
+ // goes 1 when the UART finished transmitting
+ output reg tx_transmitted,
+ // the actual UART transmitter output
+ output reg tx_signal
+ );
+
+ // Internal TX data (latched from tx_data_in)
+ reg [7:0] tx_data;
+
+ reg [3:0] state;
+ `define IDLE 0
+ `define START 1
+ `define BIT0 2
+ `define BIT1 3
+ `define BIT2 4
+ `define BIT3 5
+ `define BIT4 6
+ `define BIT5 7
+ `define BIT6 8
+ `define BIT7 9
+ `define STOP 10
+
+ always @(posedge tx_clock)
+ begin
+ if (reset) begin
+ state <= `IDLE;
+ tx_signal <= 1;
+ tx_data <= 0;
+ tx_transmitted <= 1;
+ end else begin
+ case (state)
+ `IDLE: begin
+ if (tx_data_latch)
+ begin
+ tx_data <= tx_data_in;
+ state <= `START;
+ tx_transmitted <= 0;
+ end
+ end
+ `START: begin
+ tx_signal <= 0;
+ state <= `BIT0;
+ end
+ `BIT0: begin
+ tx_signal <= tx_data[0];
+ state <= `BIT1;
+ end
+ `BIT1: begin
+ tx_signal <= tx_data[1];
+ state <= `BIT2;
+ end
+ `BIT2: begin
+ tx_signal <= tx_data[2];
+ state <= `BIT3;
+ end
+ `BIT3: begin
+ tx_signal <= tx_data[3];
+ state <= `BIT4;
+ end
+ `BIT4: begin
+ tx_signal <= tx_data[4];
+ state <= `BIT5;
+ end
+ `BIT5: begin
+ tx_signal <= tx_data[5];
+ state <= `BIT6;
+ end
+ `BIT6: begin
+ tx_signal <= tx_data[6];
+ state <= `BIT7;
+ end
+ `BIT7: begin
+ tx_signal <= tx_data[7];
+ state <= `STOP;
+ end
+ `STOP: begin
+ tx_signal <= 1;
+ state <= `IDLE;
+ tx_transmitted <= 1;
+ end
+ endcase
+ end
+ end
+
+endmodule