summaryrefslogtreecommitdiffstats
path: root/uart.v
diff options
context:
space:
mode:
authorSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
committerSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
commit5d207884e0216dbe916e835df368d194e76116cc (patch)
tree55335248de2db24adb21f5b0897c8bd16831c06d /uart.v
parentec6c4a0f90d9eb10b6c036b27245a05ae1d38ee6 (diff)
downloadaamux-dumper-5d207884e0216dbe916e835df368d194e76116cc.tar.gz
aamux-dumper-5d207884e0216dbe916e835df368d194e76116cc.tar.bz2
aamux-dumper-5d207884e0216dbe916e835df368d194e76116cc.zip
Dumps!
Diffstat (limited to 'uart.v')
-rw-r--r--uart.v102
1 files changed, 84 insertions, 18 deletions
diff --git a/uart.v b/uart.v
index 4e7432a..52cbe45 100644
--- a/uart.v
+++ b/uart.v
@@ -12,7 +12,7 @@ module uart_controller(
input tx_data_latch,
// baud rate clock
- input tx_clock,
+ input clock,
// reset line
input reset,
@@ -20,13 +20,20 @@ module uart_controller(
// goes 1 when the UART finished transmitting
output reg tx_transmitted,
// the actual UART transmitter output
- output reg tx_signal
+ output reg tx_signal,
+
+ output reg rx_present,
+ input rx_present_clear,
+ output reg [7:0] rx_data,
+
+ input rx_signal
);
// Internal TX data (latched from tx_data_in)
reg [7:0] tx_data;
- reg [3:0] state;
+ reg [3:0] tx_state;
+ reg [3:0] rx_state;
`define IDLE 0
`define START 1
`define BIT0 2
@@ -38,63 +45,122 @@ module uart_controller(
`define BIT6 8
`define BIT7 9
`define STOP 10
-
- always @(posedge tx_clock)
+
+ /// Receiver
+ always @(posedge clock)
+ begin
+ if (reset) begin
+ rx_state <= `IDLE;
+ rx_present <= 0;
+ rx_data <= 0;
+ end else begin
+ if (rx_present_clear)
+ rx_present <= 0;
+ case (rx_state)
+ `IDLE: begin
+ if (!rx_signal) begin
+ // We received a start bit
+ rx_state <= `BIT0;
+ rx_present <= 0;
+ end
+ end
+ `BIT0: begin
+ rx_data[0] <= rx_signal;
+ rx_state <= `BIT1;
+ end
+ `BIT1: begin
+ rx_data[1] <= rx_signal;
+ rx_state <= `BIT2;
+ end
+ `BIT2: begin
+ rx_data[2] <= rx_signal;
+ rx_state <= `BIT3;
+ end
+ `BIT3: begin
+ rx_data[3] <= rx_signal;
+ rx_state <= `BIT4;
+ end
+ `BIT4: begin
+ rx_data[4] <= rx_signal;
+ rx_state <= `BIT5;
+ end
+ `BIT5: begin
+ rx_data[5] <= rx_signal;
+ rx_state <= `BIT6;
+ end
+ `BIT6: begin
+ rx_data[6] <= rx_signal;
+ rx_state <= `BIT7;
+ end
+ `BIT7: begin
+ rx_data[7] <= rx_signal;
+ rx_state <= `STOP;
+ end
+ `STOP: begin
+ rx_present <= 1;
+ rx_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+ /// Transmitter
+ always @(posedge clock)
begin
if (reset) begin
- state <= `IDLE;
+ tx_state <= `IDLE;
tx_signal <= 1;
tx_data <= 0;
tx_transmitted <= 1;
end else begin
- case (state)
+ case (tx_state)
`IDLE: begin
if (tx_data_latch)
begin
tx_data <= tx_data_in;
- state <= `START;
+ tx_state <= `START;
tx_transmitted <= 0;
end
end
`START: begin
tx_signal <= 0;
- state <= `BIT0;
+ tx_state <= `BIT0;
end
`BIT0: begin
tx_signal <= tx_data[0];
- state <= `BIT1;
+ tx_state <= `BIT1;
end
`BIT1: begin
tx_signal <= tx_data[1];
- state <= `BIT2;
+ tx_state <= `BIT2;
end
`BIT2: begin
tx_signal <= tx_data[2];
- state <= `BIT3;
+ tx_state <= `BIT3;
end
`BIT3: begin
tx_signal <= tx_data[3];
- state <= `BIT4;
+ tx_state <= `BIT4;
end
`BIT4: begin
tx_signal <= tx_data[4];
- state <= `BIT5;
+ tx_state <= `BIT5;
end
`BIT5: begin
tx_signal <= tx_data[5];
- state <= `BIT6;
+ tx_state <= `BIT6;
end
`BIT6: begin
tx_signal <= tx_data[6];
- state <= `BIT7;
+ tx_state <= `BIT7;
end
`BIT7: begin
tx_signal <= tx_data[7];
- state <= `STOP;
+ tx_state <= `STOP;
end
`STOP: begin
tx_signal <= 1;
- state <= `IDLE;
+ tx_state <= `IDLE;
tx_transmitted <= 1;
end
endcase