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authorSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
committerSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
commit5d207884e0216dbe916e835df368d194e76116cc (patch)
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+`timescale 1ns / 1ps
+
+// Copyright (c) 2014 Sergiusz 'q3k' Bazański <sergiusz@baznaski.pl>
+// Released under the 2-clause BSD license - see the COPYING file
+
+module sevenseg(
+ // Value to be displayed (0-FFFF)
+ input [15:0] value,
+ output reg [6:0] segments,
+ output reg [3:0] anodes,
+ input sys_clock,
+ input reset
+ );
+
+ reg [1:0] current_anode;
+ wire [3:0] current_digit[0:3];
+ assign current_digit[0] = value[3:0];
+ assign current_digit[1] = value[7:4];
+ assign current_digit[2] = value[11:8];
+ assign current_digit[3] = value[15:12];
+
+ reg [10:0] clock_counter;
+ reg clock;
+
+ always @(posedge sys_clock)
+ begin
+ if (clock_counter >= 1024)
+ begin
+ clock_counter <= 0;
+ clock <= !clock;
+ end else begin
+ clock_counter <= clock_counter + 1;
+ end
+ end
+
+ always @(posedge clock)
+ begin
+ if (reset) begin
+ segments <= 0;
+ anodes <= 0;
+ current_anode <= 0;
+ end else begin
+ current_anode <= current_anode + 1;
+ anodes <= ~(1 << (3-current_anode));
+ case (current_digit[current_anode])
+ 4'h0: segments <= 7'b1000000;
+ 4'h1: segments <= 7'b1111001;
+ 4'h2: segments <= 7'b0100100;
+ 4'h3: segments <= 7'b0110000;
+ 4'h4: segments <= 7'b0011001;
+ 4'h5: segments <= 7'b0010010;
+ 4'h6: segments <= 7'b0000010;
+ 4'h7: segments <= 7'b1111000;
+ 4'h8: segments <= 7'b0000000;
+ 4'h9: segments <= 7'b0011000;
+ 4'hA: segments <= 7'b0001000;
+ 4'hB: segments <= 7'b0000011;
+ 4'hC: segments <= 7'b1000110;
+ 4'hD: segments <= 7'b0100001;
+ 4'hE: segments <= 7'b0000110;
+ 4'hF: segments <= 7'b0001110;
+ default: segments <= 7'b0110110;
+ endcase
+ end
+ end
+
+endmodule