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authorSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
committerSergiusz 'q3k' Bazański <q3k@q3k.org>2014-01-05 22:44:56 +0100
commit5d207884e0216dbe916e835df368d194e76116cc (patch)
tree55335248de2db24adb21f5b0897c8bd16831c06d /aamux_controller.v
parentec6c4a0f90d9eb10b6c036b27245a05ae1d38ee6 (diff)
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Diffstat (limited to 'aamux_controller.v')
-rw-r--r--aamux_controller.v73
1 files changed, 58 insertions, 15 deletions
diff --git a/aamux_controller.v b/aamux_controller.v
index 1e06a09..8408f99 100644
--- a/aamux_controller.v
+++ b/aamux_controller.v
@@ -4,6 +4,7 @@
`timescale 1ns / 1ps
`include "uart.v"
+`include "sevenseg.v"
module aamux_controller(
// To the BIOS chip
@@ -22,7 +23,11 @@ module aamux_controller(
// UART TX&RX
output uart_signal_tx,
- input uart_signal_rx
+ input uart_signal_rx,
+
+ // Seven-segment display
+ output [6:0] segments,
+ output [3:0] segments_anodes
);
/// Clocks
@@ -35,30 +40,49 @@ module aamux_controller(
/// UART
reg uart_latch;
+ wire uart_received;
+ reg uart_received_clear;
+ wire [7:0] uart_rx;
wire uart_transmitted;
uart_controller uart(
.tx_data_in (data),
.tx_data_latch (uart_latch),
- .tx_clock (uart_clock),
+ .clock (uart_clock),
.reset (reset),
.tx_transmitted (uart_transmitted),
- .tx_signal (uart_signal));
+ .tx_signal (uart_signal_tx),
+ .rx_present (uart_received),
+ .rx_present_clear (uart_received_clear),
+ .rx_data (uart_rx),
+ .rx_signal (uart_signal_rx));
+
+ /// Seven-segment display
+ reg [15:0] to_display;
+ sevenseg display (
+ .value (to_display),
+ .segments (segments),
+ .anodes (segments_anodes),
+ .sys_clock (sys_clock),
+ .reset (reset));
/// State machine
reg [2:0] state;
- `define ASSERT_ROW 0
- `define ROW_LATCH 1
- `define ASSERT_COL 2
- `define COL_LATCH 3
- `define WAITING 4
- `define OUTPUT 5
- `define OUTPUT_WAIT 6
-
+ `define WAIT_CMD 0
+ `define ASSERT_ROW 1
+ `define ROW_LATCH 2
+ `define ASSERT_COL 3
+ `define COL_LATCH 4
+ `define WAITING 5
+ `define OUTPUT 6
+ `define OUTPUT_WAIT 7
+ //assign leds = (1 << state);
+ assign leds = uart_received;
+ /// Address from which we will be reading, and
+ // how many bytes are left
reg [21:0] read_address;
- assign leds = read_address[21:14];
-
+ reg [16:0] bytes_left;
/// sys_clock division into clock and uart_clock
always @(posedge sys_clock) begin
@@ -74,12 +98,25 @@ module aamux_controller(
/// Main state machine code
always @(posedge clock) begin
if (reset) begin
- state <= `ASSERT_ROW;
+ // Reset state
+ state <= `WAIT_CMD;
read_address <= 0;
+ bytes_left <= 0;
rowcol <= 1;
uart_latch <= 0;
+ to_display <= 16'hDEAD;
+ uart_received_clear <= 0;
end else begin
case (state)
+ `WAIT_CMD: begin
+ if (uart_received) begin
+ state <= `ASSERT_ROW;
+ read_address <= uart_rx * 65536;
+ bytes_left <= 'h10000;
+ uart_received_clear <= 1;
+ end else
+ to_display <= 16'hDEAD;
+ end
`ASSERT_ROW: begin
address <= read_address[10:0];
state <= `ROW_LATCH;
@@ -112,8 +149,14 @@ module aamux_controller(
`OUTPUT_WAIT: begin
if (!uart_transmitted) begin
uart_latch <= 0;
- state <= `ASSERT_ROW;
+ to_display <= bytes_left;
read_address <= read_address + 1;
+ bytes_left <= bytes_left - 1;
+ if (bytes_left - 1 == 0) begin
+ uart_received_clear <= 0;
+ state <= `WAIT_CMD;
+ end else
+ state <= `ASSERT_ROW;
end
end
endcase