216 lines
7.0 KiB
C
Executable File
216 lines
7.0 KiB
C
Executable File
#ifndef __APIC_H__
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#define __APIC_H__
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#include "types.h"
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// To write to the IMCR (interrupt mode configuration register), you need two
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// IO ports: APIC_IMCR_CTRL, and APIC_IMCR_DATA. First you output APIC_IMCR_SEL
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// to _CTRL, and then you can write to _DATA. The possible values are:
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// o 0x00 - Default, bypass the APIC
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// o 0x01 - Pass NMI and 8259A interrupts through the APIC
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#define APIC_IMCR_CTRL 0x22
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#define APIC_IMCR_DATA 0x23
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#define APIC_IMCR_SEL 0x70
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void apic_enable_lapic(void);
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// The memory mapped structure of the LAPIC
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typedef struct {
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struct { u32 __reserved[4]; } __reserved01; // 0x0000
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struct { u32 __reserved[4]; } __reserved02; // 0x0010
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struct {
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u32 __reserved1 : 24,
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ID : 4,
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__reserved2 : 4;
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u32 __reserved3[3];
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} ID; // 0x0020
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const struct {
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u32 Version : 8,
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__reserved1 : 8,
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MaxLVT : 8,
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__reserved2 : 8;
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u32 __reserved[3];
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} Version; // 0x0030
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struct { u32 __reserved[4]; } __reserved03; // 0x0040
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struct { u32 __reserved[4]; } __reserved04; // 0x0050
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struct { u32 __reserved[4]; } __reserved05; // 0x0060
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struct { u32 __reserved[4]; } __reserved06; // 0x0070
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struct {
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u32 Priority : 8,
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__reserved1 : 24;
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u32 __reserved2[3];
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} TPR; // 0x0080
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const struct {
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u32 Priority : 8,
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__reserved1 : 24;
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u32 __reserved2[3];
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} APR; // 0x0090
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const struct {
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u32 Priority : 8,
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__reserved1 : 24;
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u32 __reserved2[3];
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} PPR; // 0x00A0
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struct {
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u32 EOI;
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u32 __reserved[3];
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} EOI; // 0x00B0
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struct { u32 __reserved[4]; } __reserved07; // 0x00C0
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struct {
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u32 __reserved1 : 24,
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Destination : 8;
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u32 __reserved2[3];
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} LDR; // 0x00D0
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struct {
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u32 __reserved1 : 28,
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Model : 4;
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u32 __reserved2[3];
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} DFR; // 0x00E0
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struct {
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u32 SpuriousVector : 8,
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APICEnabled : 1,
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FocusCPU : 1,
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__reserved1 : 22;
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u32 __reserved2[3];
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} SVR; // 0x00F0
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struct {
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u32 Bitfield;
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u32 __reserved[3];
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} ISR[8]; // 0x0100
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struct {
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u32 Bitfield;
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u32 __reserved[3];
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} TMR[8]; // 0x0180
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union {
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struct {
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u32 SendCSError : 1,
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ReceiveCSError : 1,
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SendAcceptError : 1,
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ReceiveAcceptError : 1,
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__reserved1 : 1,
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SendIllegalVector : 1,
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ReceiveIllegalVector : 1,
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IllegalRegisterAddress : 1,
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__reserved2 : 24;
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u32 __reserved3[3];
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} ErrorBits;
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struct {
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u32 Errors;
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u32 __reserved[3];
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} AllErrors;
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} ESR; // 0x0280
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struct { u32 __reserved[4]; } __reserved08; // 0x0290
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struct { u32 __reserved[4]; } __reserved09; // 0x02A0
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struct { u32 __reserved[4]; } __reserved10; // 0x02B0
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struct { u32 __reserved[4]; } __reserved11; // 0x02C0
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struct { u32 __reserved[4]; } __reserved12; // 0x02D0
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struct { u32 __reserved[4]; } __reserved13; // 0x02E0
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struct { u32 __reserved[4]; } __reserved14; // 0x02F0
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struct {
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u32 Vector : 8,
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DeliveryMode : 3,
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DestinationMode : 1,
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DeliveryStatus : 1,
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__reserved1 : 1,
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level : 1,
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trigger : 1,
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__reserved2 : 2,
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shorthand : 2,
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__reserved3 : 12;
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u32 __reserved4[3];
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} ICR1; // 0x0300
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struct {
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u32 __reserved1 : 24,
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PhysicalDestination : 4,
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__reserved2 : 4;
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u32 __reserved3 : 24,
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VirtualDestination : 8;
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u32 __reserved[3];
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} ICR2; // 0x0310
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struct {
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u32 Vector : 8,
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__reserved1 : 4,
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DeliveryStatus : 1,
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__reserved2 : 3,
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Mask : 1,
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TimerMode : 1,
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__reserved3 : 12;
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u32 __reserved4[3];
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} LVTTimer; // 0x0320
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struct {
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u32 Vector : 8,
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DeliveryMode : 3,
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__reserved1 : 1,
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DeliveryStatus : 1,
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__reserved2 : 3,
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Mask : 1,
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__reserved3 : 15;
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u32 __reserved4[3];
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} LVTThermal; // 0x0330
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struct {
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u32 Vector : 8,
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DeliveryMode : 3,
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__reserved1 : 1,
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DeliveryStatus : 1,
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__reserved2 : 3,
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Mask : 1,
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__reserved3 : 15;
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u32 __reserved4[3];
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} LVTPerformanceCounter; // 0x0340
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struct {
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u32 Vector : 8,
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DeliveryMode : 3,
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__reserved1 : 1,
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DeliveryStatus : 1,
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Polarity : 1,
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RemoteIRR : 1,
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Trigger : 1,
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Mask : 1,
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__reserved2 : 15;
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u32 __reserved3[3];
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} LVTLINT0; // 0x0350
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struct {
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u32 Vector : 8,
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DeliveryMode : 3,
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__reserved1 : 1,
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DeliveryStatus : 1,
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Polarity : 1,
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RemoteIRR : 1,
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Trigger : 1,
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Mask : 1,
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__reserved2 : 15;
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u32 __reserved3[3];
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} LVTLINT1; // 0x0360
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struct {
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u32 Vector : 8,
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__reserved1 : 4,
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DeliveryStatus : 1,
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__reserved2 : 3,
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Mask : 1,
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__reserved3 : 15;
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u32 __reserved4[3];
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} LVTError; // 0x0370
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struct {
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u32 InitialCount;
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u32 __reserved[3];
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} TimerICR; // 0x0380
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struct {
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u32 CurrentCount;
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u32 __reserved[3];
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} TimerCCR; // 0x0390
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struct { u32 __reserved[4]; } __reserved15; // 0x03A0
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struct { u32 __reserved[4]; } __reserved16; // 0x03B0
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struct { u32 __reserved[4]; } __reserved17; // 0x03C0
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struct { u32 __reserved[4]; } __reserved18; // 0x03D0
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struct {
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u32 Divisor : 4,
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__reserved1 : 28;
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u32 __reserved2[3];
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} TimerDCR; // 0x3E0
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struct { u32 __reserved[4]; } __reserved19; // 0x3F0
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// phew.
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} __attribute__((packed)) T_APIC_LAPIC;
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#endif
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