149 lines
6.1 KiB
Verilog
149 lines
6.1 KiB
Verilog
module sdram_driver_v2 #
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(
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parameter COL_WIDTH = 8 ,//2^8 = 256 addresses in each colum
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parameter ROW_WIDTH = 12 ,//2^12 = 4096 addresses in each bank
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parameter BANK_WIDTH = 2 ,//2^2 = 4 banks in a single chip
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parameter DQ_WIDTH = 8 ,//8 bit Data Bus for one chip
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parameter [12:0] SDRAM_MR = 13'h0037 ,//Full Page Burst,Latency=3,Burst Read and Burst Write,Standard mode
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parameter DDR_PRIMITIVE_TYPE = "VIRTEX5" //FPGA is Virtex-5 serirals
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)
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(
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clk0 ,//The main clock of the control system
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clk1 ,//have the same period of clk0, but the phase is shifted
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rst_n ,//A low voltage may bring the control system to an oringinal state,and the data in SDRAM may be damaged
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user_command_req ,//The user want to send a read/write command,active HIGH
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user_command_gnt ,//The state machine have accept the user's read/write command
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user_rd0_wr1 ,//HIGH voltage means read and a low means write,synchronous to "user_command_req"
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user_burst_length,//Express the read/write lenghth of each command,synchronous to "user_command_req"
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user_start_addr ,//the user's read/write address,synchronous to "user_command_req"
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Tx_fifo_rd_en ,//used in the user's write command,this port is synchronous to "clk0"
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Tx_fifo_rd_data ,//the user write data to the fifo,synchronous to "clk0"
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sdram_data_valid,//tell the user that valid read data is coming,active HIGH
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sdram_rd_data ,//synchronous to sdram_data_valid
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sdram_clk ,//connected to the CLK port of SDRAM
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sdram_cke ,//connected to the CKE port of SDRAM
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sdram_cs_n ,//connected to the CS_n port of SDRAM
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sdram_ras_n ,//connected to the RAS_n port of SDRAM
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sdram_cas_n ,//connected to the CAS_n port of SDRAM
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sdram_we_n ,//connected to the WE_n port of SDRAM
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sdram_ba ,//connected to the BA port of SDRAM
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sdram_addr ,//connected to the ADDR port of SDRAM
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sdram_dqm ,//connected to the DQM port of SDRAM
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sdram_dq //connected to the DQ port of SDRAM
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);
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input clk0;
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input clk1;
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input rst_n;
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input user_command_req;
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output user_command_gnt;
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input user_rd0_wr1;
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input [COL_WIDTH-1:0] user_burst_length;
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input [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
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output Tx_fifo_rd_en;
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input [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] Tx_fifo_rd_data;
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output sdram_data_valid;
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output [DQ_WIDTH-1 : 0] sdram_rd_data;
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output sdram_clk ;
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output sdram_cke ;
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output sdram_cs_n ;
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output sdram_ras_n;
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output sdram_cas_n;
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output sdram_we_n ;
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output [BANK_WIDTH-1 : 0] sdram_ba ;
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output [ROW_WIDTH-1 : 0] sdram_addr ;
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output [DQ_WIDTH/8-1: 0] sdram_dqm ;
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inout [DQ_WIDTH-1 : 0] sdram_dq ;
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wire c0_sdram_cke;
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wire c0_sdram_cs_n;
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wire c0_sdram_ras_n;
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wire c0_sdram_cas_n;
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wire c0_sdram_we_n;
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wire [BANK_WIDTH-1 : 0] c0_sdram_ba;
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wire [ROW_WIDTH-1 : 0] c0_sdram_addr;
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wire c0_sdram_dq_out_en;
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wire [DQ_WIDTH/8-1: 0] c0_sdram_dqm;
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wire [DQ_WIDTH-1 : 0] c0_sdram_dq_out;
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wire [DQ_WIDTH-1 : 0] c0_sdram_dq_in;
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sdram_ctrl #
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(
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.COL_WIDTH (COL_WIDTH ),
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.ROW_WIDTH (ROW_WIDTH ),
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.BANK_WIDTH (BANK_WIDTH ),
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.DQ_WIDTH (DQ_WIDTH ),
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.SDRAM_MR (SDRAM_MR )
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)
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u_sdram_ctrl(
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.clk (clk0 ),//The main clock of the control system
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.rst_n(rst_n),//A low voltage may bring the control system to an oringinal state,but the data in SDRAM may be damaged
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.user_command_req (user_command_req ),//The user want to send a read/write command,active HIGH
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.user_command_gnt (user_command_gnt ),//The state machine have accept the user's read/write command
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.user_rd0_wr1 (user_rd0_wr1 ),//HIGH voltage means read and a low means write,synchronous to "user_command_req"
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.user_burst_length(user_burst_length),//Express the read/write lenghth of each command,synchronous to "user_command_req"
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.user_start_addr (user_start_addr ),//the user's read/write address,synchronous to "user_command_req"
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.Tx_fifo_rd_en (Tx_fifo_rd_en ),//used in the user's write command,this port is synchronous to "clk0"
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.Tx_fifo_rd_data (Tx_fifo_rd_data ),//the user write data to the fifo,synchronous to "clk0"
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.sdram_cke (c0_sdram_cke ),
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.sdram_cs_n (c0_sdram_cs_n ),
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.sdram_ras_n (c0_sdram_ras_n ),
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.sdram_cas_n (c0_sdram_cas_n ),
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.sdram_we_n (c0_sdram_we_n ),
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.sdram_ba (c0_sdram_ba ),
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.sdram_addr (c0_sdram_addr ),
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.sdram_dq_out_en(c0_sdram_dq_out_en),
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.sdram_dqm (c0_sdram_dqm ),
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.sdram_dq_out (c0_sdram_dq_out ),
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.sdram_dq_in (c0_sdram_dq_in ),
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.sdram_data_valid(sdram_data_valid),//tell the user that valid read data is coming,active HIGH
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.sdram_rd_data (sdram_rd_data ) //synchronous to sdram_data_valid
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);
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sdram_io #
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(
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.ROW_WIDTH (ROW_WIDTH ),
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.BANK_WIDTH (BANK_WIDTH ),
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.DQ_WIDTH (DQ_WIDTH ),
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.DDR_PRIMITIVE_TYPE(DDR_PRIMITIVE_TYPE)
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)
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u_sdram_io
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(
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.clk0(clk0),
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.clk1(clk1),
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.c0_sdram_cke (c0_sdram_cke ),
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.c0_sdram_cs_n (c0_sdram_cs_n ),
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.c0_sdram_ras_n (c0_sdram_ras_n ),
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.c0_sdram_cas_n (c0_sdram_cas_n ),
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.c0_sdram_we_n (c0_sdram_we_n ),
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.c0_sdram_ba (c0_sdram_ba ),
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.c0_sdram_addr (c0_sdram_addr ),
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.c0_sdram_dq_out_en(c0_sdram_dq_out_en),
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.c0_sdram_dqm (c0_sdram_dqm ),
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.c0_sdram_dq_out (c0_sdram_dq_out ),
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.c0_sdram_dq_in (c0_sdram_dq_in ),
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.c1_sdram_clk (sdram_clk ),
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.c1_sdram_cke (sdram_cke ),
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.c1_sdram_cs_n (sdram_cs_n ),
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.c1_sdram_ras_n (sdram_ras_n),
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.c1_sdram_cas_n (sdram_cas_n),
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.c1_sdram_we_n (sdram_we_n ),
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.c1_sdram_ba (sdram_ba ),
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.c1_sdram_addr (sdram_addr ),
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.c1_sdram_dqm (sdram_dqm ),
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.c1_sdram_dq (sdram_dq )
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);
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endmodule
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