fifo, lolchina cleanup
This commit is contained in:
Bartosz Stebel
parent
19bbc7b8cc
commit
49345daefb
8 changed files with 816 additions and 188 deletions
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@ -1,3 +1,5 @@
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CONFIG VCCAUX=3.3;
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NET "*" IOSTANDARD = LVCMOS33;
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#CLOCK
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#NET "clk24m" LOC = "P56";
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NET "clk50m" LOC = "P55";
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213
ipcore_dir/Tx_fifo.xco
Normal file
213
ipcore_dir/Tx_fifo.xco
Normal file
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@ -0,0 +1,213 @@
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##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Wed Feb 25 21:54:42 2015
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:fifo_generator:9.3
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
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# END Select
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# BEGIN Parameters
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CSET add_ngc_constraint_axi=false
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CSET almost_empty_flag=false
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CSET almost_full_flag=false
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CSET aruser_width=1
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CSET awuser_width=1
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CSET axi_address_width=32
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CSET axi_data_width=64
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CSET axi_type=AXI4_Stream
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CSET axis_type=FIFO
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CSET buser_width=1
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CSET clock_enable_type=Slave_Interface_Clock_Enable
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CSET clock_type_axi=Common_Clock
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CSET component_name=Tx_fifo
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CSET data_count=false
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CSET data_count_width=9
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CSET disable_timing_violations=false
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CSET disable_timing_violations_axi=false
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CSET dout_reset_value=0
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CSET empty_threshold_assert_value=2
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CSET empty_threshold_assert_value_axis=1022
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CSET empty_threshold_assert_value_rach=1022
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CSET empty_threshold_assert_value_rdch=1022
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CSET empty_threshold_assert_value_wach=1022
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CSET empty_threshold_assert_value_wdch=1022
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CSET empty_threshold_assert_value_wrch=1022
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CSET empty_threshold_negate_value=3
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CSET enable_aruser=false
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CSET enable_awuser=false
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CSET enable_buser=false
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CSET enable_common_overflow=false
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CSET enable_common_underflow=false
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CSET enable_data_counts_axis=false
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CSET enable_data_counts_rach=false
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CSET enable_data_counts_rdch=false
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CSET enable_data_counts_wach=false
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CSET enable_data_counts_wdch=false
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CSET enable_data_counts_wrch=false
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CSET enable_ecc=false
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CSET enable_ecc_axis=false
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CSET enable_ecc_rach=false
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CSET enable_ecc_rdch=false
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CSET enable_ecc_wach=false
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CSET enable_ecc_wdch=false
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CSET enable_ecc_wrch=false
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CSET enable_read_channel=false
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CSET enable_read_pointer_increment_by2=false
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CSET enable_reset_synchronization=true
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CSET enable_ruser=false
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CSET enable_tdata=false
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CSET enable_tdest=false
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CSET enable_tid=false
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CSET enable_tkeep=false
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CSET enable_tlast=false
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CSET enable_tready=true
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CSET enable_tstrobe=false
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CSET enable_tuser=false
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CSET enable_write_channel=false
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CSET enable_wuser=false
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CSET fifo_application_type_axis=Data_FIFO
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CSET fifo_application_type_rach=Data_FIFO
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CSET fifo_application_type_rdch=Data_FIFO
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CSET fifo_application_type_wach=Data_FIFO
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CSET fifo_application_type_wdch=Data_FIFO
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CSET fifo_application_type_wrch=Data_FIFO
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CSET fifo_implementation=Common_Clock_Block_RAM
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CSET fifo_implementation_axis=Common_Clock_Block_RAM
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CSET fifo_implementation_rach=Common_Clock_Block_RAM
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CSET fifo_implementation_rdch=Common_Clock_Block_RAM
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CSET fifo_implementation_wach=Common_Clock_Block_RAM
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CSET fifo_implementation_wdch=Common_Clock_Block_RAM
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CSET fifo_implementation_wrch=Common_Clock_Block_RAM
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CSET full_flags_reset_value=0
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CSET full_threshold_assert_value=510
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CSET full_threshold_assert_value_axis=1023
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CSET full_threshold_assert_value_rach=1023
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CSET full_threshold_assert_value_rdch=1023
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CSET full_threshold_assert_value_wach=1023
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CSET full_threshold_assert_value_wdch=1023
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CSET full_threshold_assert_value_wrch=1023
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CSET full_threshold_negate_value=509
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CSET id_width=4
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CSET inject_dbit_error=false
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CSET inject_dbit_error_axis=false
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CSET inject_dbit_error_rach=false
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CSET inject_dbit_error_rdch=false
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CSET inject_dbit_error_wach=false
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CSET inject_dbit_error_wdch=false
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CSET inject_dbit_error_wrch=false
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CSET inject_sbit_error=false
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CSET inject_sbit_error_axis=false
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CSET inject_sbit_error_rach=false
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CSET inject_sbit_error_rdch=false
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CSET inject_sbit_error_wach=false
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CSET inject_sbit_error_wdch=false
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CSET inject_sbit_error_wrch=false
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CSET input_data_width=18
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CSET input_depth=512
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CSET input_depth_axis=1024
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CSET input_depth_rach=16
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CSET input_depth_rdch=1024
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CSET input_depth_wach=16
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CSET input_depth_wdch=1024
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CSET input_depth_wrch=16
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CSET interface_type=Native
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CSET output_data_width=18
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CSET output_depth=512
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CSET overflow_flag=false
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CSET overflow_flag_axi=false
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CSET overflow_sense=Active_High
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CSET overflow_sense_axi=Active_High
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CSET performance_options=Standard_FIFO
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CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
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CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
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CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
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CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
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CSET programmable_full_type_axis=No_Programmable_Full_Threshold
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CSET programmable_full_type_rach=No_Programmable_Full_Threshold
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CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
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CSET programmable_full_type_wach=No_Programmable_Full_Threshold
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CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
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CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
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CSET rach_type=FIFO
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CSET rdch_type=FIFO
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CSET read_clock_frequency=1
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CSET read_data_count=false
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CSET read_data_count_width=9
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CSET register_slice_mode_axis=Fully_Registered
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CSET register_slice_mode_rach=Fully_Registered
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CSET register_slice_mode_rdch=Fully_Registered
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CSET register_slice_mode_wach=Fully_Registered
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CSET register_slice_mode_wdch=Fully_Registered
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CSET register_slice_mode_wrch=Fully_Registered
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CSET reset_pin=true
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CSET reset_type=Synchronous_Reset
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CSET ruser_width=1
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CSET synchronization_stages=2
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CSET synchronization_stages_axi=2
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CSET tdata_width=64
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CSET tdest_width=4
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CSET tid_width=8
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CSET tkeep_width=4
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CSET tstrb_width=4
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CSET tuser_width=4
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CSET underflow_flag=false
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CSET underflow_flag_axi=false
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CSET underflow_sense=Active_High
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CSET underflow_sense_axi=Active_High
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CSET use_clock_enable=false
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CSET use_dout_reset=true
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CSET use_embedded_registers=false
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CSET use_extra_logic=false
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CSET valid_flag=false
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CSET valid_sense=Active_High
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CSET wach_type=FIFO
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CSET wdch_type=FIFO
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CSET wrch_type=FIFO
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CSET write_acknowledge_flag=false
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CSET write_acknowledge_sense=Active_High
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CSET write_clock_frequency=1
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CSET write_data_count=false
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CSET write_data_count_width=9
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CSET wuser_width=1
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-11-19T12:39:56Z
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# END Extra information
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GENERATE
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# CRC: b1c22986
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73
ipcore_dir/Tx_fifo.xise
Normal file
73
ipcore_dir/Tx_fifo.xise
Normal file
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@ -0,0 +1,73 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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||||
<header>
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||||
<!-- ISE source project file created by Project Navigator. -->
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||||
<!-- -->
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||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
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||||
<!-- along with the project source files, is sufficient to open and -->
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||||
<!-- implement in ISE Project Navigator. -->
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||||
<!-- -->
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||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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||||
</header>
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||||
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="Tx_fifo.ngc" xil_pn:type="FILE_NGC">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="Tx_fifo.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Module|Tx_fifo" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="Tx_fifo.ngc" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Tx_fifo" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
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||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="Tx_fifo" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-25T22:56:07" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6946860AD50322778544D6305ECA0D9E" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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||||
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||||
<bindings/>
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||||
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<libraries/>
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||||
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<autoManagedFiles>
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||||
<!-- The following files are identified by `include statements in verilog -->
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||||
<!-- source files and are automatically managed by Project Navigator. -->
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||||
<!-- -->
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||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
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||||
<!-- project is analyzed based on files automatically identified as -->
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||||
<!-- include files. -->
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||||
</autoManagedFiles>
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||||
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||||
</project>
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||||
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@ -1,7 +1,7 @@
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##############################################################
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||||
#
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# Xilinx Core Generator version 14.7
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||||
# Date: Wed Feb 25 16:27:25 2015
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||||
# Date: Wed Feb 25 20:44:33 2015
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||||
#
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||||
##############################################################
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#
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@ -16,11 +16,11 @@
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<files>
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<file xil_pn:name="clock_pll.ucf" xil_pn:type="FILE_UCF">
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||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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||||
<file xil_pn:name="clock_pll.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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||||
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@ -28,31 +28,359 @@
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</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|clock_pll" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="clock_pll.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clock_pll" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="clock_pll" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="clock_pll_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="clock_pll_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="clock_pll_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="clock_pll_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="clock_pll" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-25T17:27:45" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E6418B99C5FE2C88C6488515605D7C90" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-02-25T21:44:49" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="EC4CD5C9A2D7DBF5FDBB3C4D4C2DD1BD" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
</file>
|
||||
<file xil_pn:name="top.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="sdram_io.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
|
||||
|
|
@ -40,11 +40,18 @@
|
|||
</file>
|
||||
<file xil_pn:name="ipcore_dir/clock_pll.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/Tx_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/clock_pll.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/Tx_fifo.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
|
|
@ -342,7 +349,7 @@
|
|||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
|
|
|
|||
244
sdram_ctrl.v
244
sdram_ctrl.v
|
|
@ -1,145 +1,107 @@
|
|||
module sdram_ctrl #
|
||||
(
|
||||
parameter COL_WIDTH = 8 ,//2^8 = 256 addresses in each colum
|
||||
parameter ROW_WIDTH = 12 ,//2^12 = 4096 addresses in each bank
|
||||
parameter BANK_WIDTH = 2 ,//2^2 = 4 banks in a single chip
|
||||
parameter DQ_WIDTH = 8 ,//8 bit Data Bus for one chip
|
||||
parameter [12:0] SDRAM_MR = 13'h0037 //Full Page Burst,Latency=3,Burst Read and Burst Write,Standard mode
|
||||
)
|
||||
(
|
||||
clk ,//The main clock of the control system
|
||||
rst_n,//A low voltage may bring the control system to an oringinal state,but the data in SDRAM may be damaged
|
||||
|
||||
user_command_req ,//The user want to send a read/write command,active HIGH
|
||||
user_command_gnt ,//The state machine have accept the user's read/write command
|
||||
user_rd0_wr1 ,//HIGH voltage means read and a low means write,synchronous to "user_command_req"
|
||||
user_burst_length,//Express the read/write lenghth of each command,synchronous to "user_command_req"
|
||||
user_start_addr ,//the user's read/write address,synchronous to "user_command_req"
|
||||
Tx_fifo_rd_en ,//used in the user's write command,this port is synchronous to "clk"
|
||||
Tx_fifo_rd_data ,//the user write data to the fifo,synchronous to "clk"
|
||||
|
||||
sdram_cke ,
|
||||
sdram_cs_n ,
|
||||
sdram_ras_n ,
|
||||
sdram_cas_n ,
|
||||
sdram_we_n ,
|
||||
sdram_ba ,
|
||||
sdram_addr ,
|
||||
sdram_dq_out_en,
|
||||
sdram_dqm ,
|
||||
sdram_dq_out ,
|
||||
sdram_dq_in ,
|
||||
|
||||
sdram_data_valid,//tell the user that valid read data is coming,active HIGH
|
||||
sdram_rd_data //synchronous to sdram_data_valid
|
||||
);
|
||||
(
|
||||
parameter COL_WIDTH = 8 ,//2^8 = 256 addresses in each colum
|
||||
parameter ROW_WIDTH = 12 ,//2^12 = 4096 addresses in each bank
|
||||
parameter BANK_WIDTH = 2 ,//2^2 = 4 banks in a single chip
|
||||
parameter DQ_WIDTH = 8 ,//8 bit Data Bus for one chip
|
||||
parameter [12:0] SDRAM_MR = 13'h0037 //Full Page Burst,Latency=3,Burst Read and Burst Write,Standard mode
|
||||
) (
|
||||
clk ,//The main clock of the control system
|
||||
rst_n,//A low voltage may bring the control system to an oringinal state,but the data in SDRAM may be damaged
|
||||
|
||||
user_command_req ,//The user want to send a read/write command,active HIGH
|
||||
user_command_gnt ,//The state machine have accept the user's read/write command
|
||||
user_rd0_wr1 ,//HIGH voltage means read and a low means write,synchronous to "user_command_req"
|
||||
user_burst_length,//Express the read/write lenghth of each command,synchronous to "user_command_req"
|
||||
user_start_addr ,//the user's read/write address,synchronous to "user_command_req"
|
||||
Tx_fifo_rd_en ,//used in the user's write command,this port is synchronous to "clk"
|
||||
Tx_fifo_rd_data ,//the user write data to the fifo,synchronous to "clk"
|
||||
|
||||
sdram_cke ,
|
||||
sdram_cs_n ,
|
||||
sdram_ras_n ,
|
||||
sdram_cas_n ,
|
||||
sdram_we_n ,
|
||||
sdram_ba ,
|
||||
sdram_addr ,
|
||||
sdram_dq_out_en,
|
||||
sdram_dqm ,
|
||||
sdram_dq_out ,
|
||||
sdram_dq_in ,
|
||||
|
||||
sdram_data_valid,//tell the user that valid read data is coming,active HIGH
|
||||
sdram_rd_data //synchronous to sdram_data_valid
|
||||
);
|
||||
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
|
||||
//1.本模块(sdram_ctrl.v)是SDRAM的核心控制逻辑，以clk作为参考时钟。另一个模块(sdram_io.v)主要是对SDRAM的IO控制接口的时序
|
||||
//做相位调整。相位的具体偏差范围跟FPGA内布线后各信号的延迟、PCB的走线情况以及SDRAM的参数有关，用户可以根据实际情况作调整。
|
||||
|
||||
//2.当user_command_req被拉高时，表示用户需要执行一个读或者写命令。user_command_req信号应该一直持续有效至
|
||||
//user_command_gnt有效。此模块会在user_command_gnt有效时采样user_rd0_wr1，user_DQM，user_burst_length，
|
||||
//user_start_addr，以决定接下来产生什么样的SDRAM操作。
|
||||
|
||||
//3.当SDRAM忙于在初始化时或是执行用户的命令或是在做自刷新时，不会理睬用户发来的任何命令。只有当user_command_gnt有效
|
||||
//有效时，才表示此模块已经接受用户的读/写请求。
|
||||
|
||||
//4.如果用户发起的是读操作，则user_rd0_wr1在user_command_req有效时，是低电平。写操作反之。
|
||||
|
||||
//5.user_burst_length表示的是对SDRAM的突发读写的长度。如果是0，表示突发长度为1，如果是511，表示突发长度
|
||||
//是512，以此类推。
|
||||
|
||||
//6.SDRAM的突发读写的最大长度是2^COL_WIDTH(2的COL_WIDTH次方)。在突发读写的时候，一定要特别留意突发的地址范围不要出现越界。
|
||||
//越界是指在一次突发中，突发的起始地址和结束地址处于不同的ROW中。如果出现越界，那么实际突发地址会回滚至当前页的起始地址，
|
||||
//而不是下一个页的起始地址。
|
||||
|
||||
//7.user_start_addr指的是本次操作中起始地址。
|
||||
|
||||
//8.对于写操作，用户需要先将待写入SDRAM的数据按顺序写入Tx_fifo中。Tx_fifo由外部模块提供，本模块仅仅负责从Tx_fifo中读数。
|
||||
//如果用户那边的速度做够快，也可以先发起写操作，再将待写入的数据存入fifo。因为此模块在接收到用户的命令后，至少需要等待6
|
||||
//个时钟周期才可能访问fifo中的内容。此fifo的深度默认为1个Page的数据。
|
||||
|
||||
//9.建议在每一次突发写之前，先将fifo清空，然后在将数字序列写入fifo。
|
||||
|
||||
//10.如果是读操作，用户在发送完命令后，还需检查sdram_data_valid信号。当sdram_data_valid有效时，表示从
|
||||
//SDRAM中读出的数据已经返回。如果突发长度为n，则sdram_data_valid会持续有效n个时钟周期。sdram_rd_data也会
|
||||
//随着时钟周期的推移而变化，它表示的是从SDRAM中读出的数据。第1个数据对应着突发的起始地址的数据，第n个数
|
||||
//据对应着突发的结束地址的数据。
|
||||
|
||||
//11.clk的最大时钟频率不能超过SDRAM器件本身的参考频率。如果用户考虑改变clk的频率，有一个参数需要注意，
|
||||
//就是控制SDRAM每次自刷新的间隔时间。当clk的频率是100MHz时，SDRAM会在每64ms内刷新8192次。如果频率变小了，
|
||||
//刷新的速率必然会变慢，如果慢到了器件所规定的最慢刷新频率，那么SDRAM内部的数据将会损坏。这时，用户可以
|
||||
//修改Refresh_Period的值以提高SDRAM的刷新速率。
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
|
||||
input user_command_req;
|
||||
output user_command_gnt;
|
||||
input user_rd0_wr1;
|
||||
input [COL_WIDTH-1:0] user_burst_length;
|
||||
input [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
|
||||
output Tx_fifo_rd_en;
|
||||
input [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] Tx_fifo_rd_data;
|
||||
|
||||
output sdram_cke;
|
||||
output sdram_cs_n;
|
||||
output sdram_ras_n;
|
||||
output sdram_cas_n;
|
||||
output sdram_we_n;
|
||||
output [BANK_WIDTH-1 : 0] sdram_ba;
|
||||
output [ROW_WIDTH-1 : 0] sdram_addr;
|
||||
output sdram_dq_out_en;
|
||||
output [DQ_WIDTH/8-1: 0] sdram_dqm;
|
||||
output [DQ_WIDTH-1 : 0] sdram_dq_out;
|
||||
input [DQ_WIDTH-1 : 0] sdram_dq_in;
|
||||
|
||||
output sdram_data_valid;
|
||||
output [DQ_WIDTH-1 : 0] sdram_rd_data;
|
||||
|
||||
parameter [9:0]
|
||||
Refresh_Period = 10'd781;//when clk is 100MHz,8192 Refresh cycles happens very 64ms
|
||||
|
||||
reg [9:0] Refresh_cnt;
|
||||
always @ (posedge clk)//account for Refresh_INT
|
||||
begin
|
||||
if(!rst_n)
|
||||
Refresh_cnt <= 10'd0;
|
||||
else if(Refresh_cnt != Refresh_Period)
|
||||
Refresh_cnt <= Refresh_cnt + 1'b1;
|
||||
else
|
||||
Refresh_cnt <= 10'd0;
|
||||
end
|
||||
|
||||
reg Refresh_INT;
|
||||
wire Refresh_INT_clear;
|
||||
always @ (posedge clk)//A refresh command should be excuted when Refresh_INT is High
|
||||
begin
|
||||
if(!rst_n)
|
||||
Refresh_INT <= 1'b0;
|
||||
else if(Refresh_cnt == Refresh_Period)
|
||||
Refresh_INT <= 1'b1;
|
||||
else if(Refresh_INT_clear)
|
||||
Refresh_INT <= 1'b0;
|
||||
end
|
||||
|
||||
wire user_INT;
|
||||
assign user_INT = user_command_req;//A read/write command should be excuted when user_INT is High
|
||||
|
||||
reg user_command_gnt;
|
||||
|
||||
reg user_rd0_wr1_buf;
|
||||
reg [COL_WIDTH-1:0] user_burst_length_buf;
|
||||
reg [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr_buf;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if(!rst_n)
|
||||
begin
|
||||
user_rd0_wr1_buf <= 1'b0;
|
||||
user_burst_length_buf <= 1'b0;
|
||||
user_start_addr_buf <= 1'b0;
|
||||
end
|
||||
else if(user_command_gnt)
|
||||
input user_command_req;
|
||||
output user_command_gnt;
|
||||
input user_rd0_wr1;
|
||||
input [COL_WIDTH-1:0] user_burst_length;
|
||||
input [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
|
||||
output Tx_fifo_rd_en;
|
||||
input [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] Tx_fifo_rd_data;
|
||||
|
||||
output sdram_cke;
|
||||
output sdram_cs_n;
|
||||
output sdram_ras_n;
|
||||
output sdram_cas_n;
|
||||
output sdram_we_n;
|
||||
output [BANK_WIDTH-1 : 0] sdram_ba;
|
||||
output [ROW_WIDTH-1 : 0] sdram_addr;
|
||||
output sdram_dq_out_en;
|
||||
output [DQ_WIDTH/8-1: 0] sdram_dqm;
|
||||
output [DQ_WIDTH-1 : 0] sdram_dq_out;
|
||||
input [DQ_WIDTH-1 : 0] sdram_dq_in;
|
||||
|
||||
output sdram_data_valid;
|
||||
output [DQ_WIDTH-1 : 0] sdram_rd_data;
|
||||
|
||||
parameter [9:0] Refresh_Period = 10'd781;//when clk is 100MHz,8192 Refresh cycles happens very 64ms
|
||||
|
||||
reg [9:0] Refresh_cnt;
|
||||
always @ (posedge clk)//account for Refresh_INT
|
||||
begin
|
||||
if(!rst_n)
|
||||
Refresh_cnt <= 10'd0;
|
||||
else if(Refresh_cnt != Refresh_Period)
|
||||
Refresh_cnt <= Refresh_cnt + 1'b1;
|
||||
else
|
||||
Refresh_cnt <= 10'd0;
|
||||
end
|
||||
|
||||
reg Refresh_INT;
|
||||
wire Refresh_INT_clear;
|
||||
always @ (posedge clk)//A refresh command should be excuted when Refresh_INT is High
|
||||
begin
|
||||
if(!rst_n)
|
||||
Refresh_INT <= 1'b0;
|
||||
else if(Refresh_cnt == Refresh_Period)
|
||||
Refresh_INT <= 1'b1;
|
||||
else if(Refresh_INT_clear)
|
||||
Refresh_INT <= 1'b0;
|
||||
end
|
||||
|
||||
wire user_INT;
|
||||
assign user_INT = user_command_req;//A read/write command should be excuted when user_INT is High
|
||||
|
||||
reg user_command_gnt;
|
||||
|
||||
reg user_rd0_wr1_buf;
|
||||
reg [COL_WIDTH-1:0] user_burst_length_buf;
|
||||
reg [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr_buf;
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if(!rst_n)
|
||||
begin
|
||||
user_rd0_wr1_buf <= 1'b0;
|
||||
user_burst_length_buf <= 1'b0;
|
||||
user_start_addr_buf <= 1'b0;
|
||||
end
|
||||
else if(user_command_gnt)
|
||||
begin
|
||||
user_rd0_wr1_buf <= user_rd0_wr1;
|
||||
user_burst_length_buf <= user_burst_length;
|
||||
|
|
@ -784,4 +746,4 @@ module sdram_ctrl #
|
|||
endtask
|
||||
//all tasks end here//
|
||||
|
||||
endmodule
|
||||
endmodule
|
||||
|
|
|
|||
117
top.v
117
top.v
|
|
@ -80,7 +80,23 @@ module top(
|
|||
|
||||
assign IO_A5 = BaudTick;
|
||||
|
||||
wire [8:0] user_burst_length;
|
||||
assign user_burst_length = 9'h1FF;
|
||||
wire user_command_gnt;
|
||||
reg user_command_req;
|
||||
wire user_rd0_wr1 = 0;
|
||||
reg [BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1 : 0] user_start_addr;
|
||||
wire sdram_data_valid;
|
||||
wire [DQ_WIDTH-1 :0] sdram_rd_data;
|
||||
|
||||
reg has_byte;
|
||||
|
||||
wire Tx_fifo_rd_en;
|
||||
reg [DQ_WIDTH/8+DQ_WIDTH-1 :0 ] txreg;
|
||||
reg Tx_fifo_wr_en;
|
||||
wire [DQ_WIDTH/8+DQ_WIDTH-1 : 0] Tx_fifo_rd_data;
|
||||
wire Tx_fifo_almost_full;
|
||||
wire Tx_fifo_almost_empty;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
|
|
@ -119,44 +135,71 @@ module top(
|
|||
end
|
||||
endcase
|
||||
|
||||
|
||||
///////////////
|
||||
txreg <= txreg + 1;
|
||||
if(Tx_fifo_wr_en)
|
||||
Tx_fifo_wr_en <= 0;
|
||||
if(!Tx_fifo_almost_full)
|
||||
Tx_fifo_wr_en <= 1;
|
||||
else
|
||||
user_command_req <= 1;
|
||||
if(user_command_req)
|
||||
user_command_req <= 0;
|
||||
|
||||
if(user_command_gnt)
|
||||
user_start_addr <= user_start_addr + 1;
|
||||
if(sdram_data_valid)
|
||||
tx_byte <= sdram_rd_data;
|
||||
end
|
||||
|
||||
sdram_driver_v2 #
|
||||
(
|
||||
.COL_WIDTH (COL_WIDTH ),
|
||||
.ROW_WIDTH (ROW_WIDTH ),
|
||||
.BANK_WIDTH (BANK_WIDTH ),
|
||||
.DQ_WIDTH (DQ_WIDTH ),
|
||||
.SDRAM_MR (SDRAM_MR ),
|
||||
.DDR_PRIMITIVE_TYPE(DDR_PRIMITIVE_TYPE)
|
||||
)
|
||||
u_sdram_driver_v2(
|
||||
.clk0(clk125),//The main clock of the control system
|
||||
.clk1(clk125_ram),//have the same period of clk, but the phase is shifted
|
||||
.rst_n(reset_n),
|
||||
|
||||
.user_command_req (user_command_req ),//The user want to send a read/write command,active HIGH
|
||||
.user_command_gnt (user_command_gnt ),//The state machine have accept the user's read/write command
|
||||
.user_rd0_wr1 (user_rd0_wr1 ),//HIGH voltage means read and a low means write,synchronous to "user_command_req"
|
||||
.user_burst_length(user_burst_length),//Express the read/write lenghth of each command,synchronous to "user_command_req"
|
||||
.user_start_addr (user_start_addr ),//the user's read/write address,synchronous to "user_command_req"
|
||||
.Tx_fifo_rd_en (Tx_fifo_rd_en ),//used in the user's write command,this port is synchronous to "clk"
|
||||
.Tx_fifo_rd_data (Tx_fifo_rd_data ),//the user write data to the fifo,synchronous to "clk"
|
||||
|
||||
.sdram_data_valid(sdram_data_valid),//tell the user that valid read data is coming,active HIGH
|
||||
.sdram_rd_data (sdram_rd_data ),//synchronous to sdram_data_valid
|
||||
|
||||
.sdram_clk (sdram_clk ),//connected to the CLK port of SDRAM
|
||||
.sdram_cke (sdram_cke ),//connected to the CKE port of SDRAM
|
||||
.sdram_cs_n (sdram_cs_n ),//connected to the CS_n port of SDRAM
|
||||
.sdram_ras_n (sdram_ras_n),//connected to the RAS_n port of SDRAM
|
||||
.sdram_cas_n (sdram_cas_n),//connected to the CAS_n port of SDRAM
|
||||
.sdram_we_n (sdram_we_n ),//connected to the WE_n port of SDRAM
|
||||
.sdram_ba (sdram_ba ),//connected to the BA port of SDRAM
|
||||
.sdram_addr (sdram_addr ),//connected to the ADDR port of SDRAM
|
||||
.sdram_dqm (sdram_dqm ),//connected to the DQM port of SDRAM
|
||||
.sdram_dq (sdram_dq ) //connected to the DQ port of SDRAM
|
||||
);
|
||||
sdram_driver_v2 #
|
||||
(
|
||||
.COL_WIDTH (COL_WIDTH ),
|
||||
.ROW_WIDTH (ROW_WIDTH ),
|
||||
.BANK_WIDTH (BANK_WIDTH ),
|
||||
.DQ_WIDTH (DQ_WIDTH ),
|
||||
.SDRAM_MR (SDRAM_MR ),
|
||||
.DDR_PRIMITIVE_TYPE(DDR_PRIMITIVE_TYPE)
|
||||
)
|
||||
u_sdram_driver_v2(
|
||||
.clk0(clk125),//The main clock of the control system
|
||||
.clk1(clk125_ram),//have the same period of clk, but the phase is shifted
|
||||
.rst_n(reset_n),
|
||||
.user_command_req(user_command_req ),//The user want to send a read/write command,active HIGH
|
||||
.user_command_gnt (user_command_gnt ),//The state machine have accept the user's read/write command
|
||||
.user_rd0_wr1 (user_rd0_wr1 ),//HIGH voltage means read and a low means write,synchronous to "user_command_req"
|
||||
.user_burst_length(user_burst_length),//Express the read/write lenghth of each command,synchronous to "user_command_req"
|
||||
.user_start_addr (user_start_addr ),//the user's read/write address,synchronous to "user_command_req"
|
||||
.Tx_fifo_rd_en (Tx_fifo_rd_en ),//used in the user's write command,this port is synchronous to "clk"
|
||||
.Tx_fifo_rd_data (Tx_fifo_rd_data ),//the user write data to the fifo,synchronous to "clk"
|
||||
|
||||
.sdram_data_valid(sdram_data_valid),//tell the user that valid read data is coming,active HIGH
|
||||
.sdram_rd_data (sdram_rd_data ),//synchronous to sdram_data_valid
|
||||
|
||||
endmodule
|
||||
.sdram_clk (sdram_clk ),//connected to the CLK port of SDRAM
|
||||
.sdram_cke (sdram_cke ),//connected to the CKE port of SDRAM
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.sdram_cs_n (sdram_cs_n ),//connected to the CS_n port of SDRAM
|
||||
.sdram_ras_n (sdram_ras_n),//connected to the RAS_n port of SDRAM
|
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.sdram_cas_n (sdram_cas_n),//connected to the CAS_n port of SDRAM
|
||||
.sdram_we_n (sdram_we_n ),//connected to the WE_n port of SDRAM
|
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.sdram_ba (sdram_ba ),//connected to the BA port of SDRAM
|
||||
.sdram_addr (sdram_addr ),//connected to the ADDR port of SDRAM
|
||||
.sdram_dqm (sdram_dqm ),//connected to the DQM port of SDRAM
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.sdram_dq (sdram_dq ) //connected to the DQ port of SDRAM
|
||||
);
|
||||
|
||||
Tx_fifo U_Tx_fifo(
|
||||
.clk (clk ), // input clk
|
||||
.srst (reset ), // input srst
|
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.din (txreg ), // input [35 : 0] din
|
||||
.wr_en (Tx_fifo_wr_en ), // input wr_en
|
||||
.rd_en (Tx_fifo_rd_en ), // input rd_en
|
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.dout (Tx_fifo_rd_data ), // output [35 : 0] dout
|
||||
.full ( ), // output full
|
||||
.empty ( ), // output empty
|
||||
.prog_full (Tx_fifo_almost_full ), // output prog_full
|
||||
.prog_empty(Tx_fifo_almost_empty) // output prog_empty
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in a new issue