diff --git a/README b/README new file mode 100644 index 0000000..0eb693b --- /dev/null +++ b/README @@ -0,0 +1,3 @@ +A tool to dump AAMux FWH BIOS flashes. + +And some Toshiba R100 dumps in dumps/*.bin (a „block” is 64kbytes, from 0x00000 to 0x3fffff. diff --git a/aamux_controller.ucf b/aamux_controller.ucf index 67c1583..5c10066 100644 --- a/aamux_controller.ucf +++ b/aamux_controller.ucf @@ -1,6 +1,5 @@ # PlanAhead Generated physical constraints - NET "address[10]" LOC = D5; NET "address[9]" LOC = D6; NET "address[8]" LOC = E7; @@ -33,4 +32,57 @@ NET "leds[6]" LOC = P12; NET "leds[7]" LOC = P11; NET "reset" LOC = L14; NET "uart_signal_tx" LOC = B14; -NET "uart_signal_rx" LOC = A13; \ No newline at end of file +NET "uart_signal_rx" LOC = A13; + +NET "segments[0]" LOC = E14; +NET "segments[1]" LOC = G13; +NET "segments[2]" LOC = N15; +NET "segments[3]" LOC = P15; +NET "segments[4]" LOC = R16; +NET "segments[5]" LOC = F13; +NET "segments[6]" LOC = N16; + +NET "segments_anodes[0]" LOC = E13; +NET "segments_anodes[1]" LOC = F14; +NET "segments_anodes[2]" LOC = G14; +NET "segments_anodes[3]" LOC = D14; +#pin2ucf - Sun Jan 05 22:13:31 2014 +#The following constraints were newly added +NET "address<3>" LOC = B5; +NET "address<4>" LOC = B4; +NET "address<5>" LOC = D10; +NET "address<6>" LOC = D8; +NET "address<7>" LOC = D7; +NET "address<8>" LOC = E7; +NET "address<9>" LOC = D6; +NET "data<0>" LOC = A5; +NET "data<1>" LOC = A4; +NET "data<2>" LOC = A3; +NET "data<3>" LOC = C9; +NET "segments_anodes<0>" LOC = E13; +NET "data<4>" LOC = C8; +NET "segments_anodes<1>" LOC = F14; +NET "data<5>" LOC = C7; +NET "segments_anodes<2>" LOC = G14; +NET "data<6>" LOC = C6; +NET "segments_anodes<3>" LOC = D14; +NET "data<7>" LOC = C5; +NET "segments<0>" LOC = E14; +NET "segments<1>" LOC = G13; +NET "segments<2>" LOC = N15; +NET "segments<3>" LOC = P15; +NET "leds<0>" LOC = K12; +NET "segments<4>" LOC = R16; +NET "leds<1>" LOC = P14; +NET "segments<5>" LOC = F13; +NET "leds<2>" LOC = L12; +NET "segments<6>" LOC = N16; +NET "leds<3>" LOC = N14; +NET "leds<4>" LOC = P13; +NET "leds<5>" LOC = N12; +NET "leds<6>" LOC = P12; +NET "address<10>" LOC = D5; +NET "leds<7>" LOC = P11; +NET "address<0>" LOC = A8; +NET "address<1>" LOC = A7; +NET "address<2>" LOC = B6; diff --git a/aamux_controller.v b/aamux_controller.v index 1e06a09..8408f99 100644 --- a/aamux_controller.v +++ b/aamux_controller.v @@ -4,6 +4,7 @@ `timescale 1ns / 1ps `include "uart.v" +`include "sevenseg.v" module aamux_controller( // To the BIOS chip @@ -22,7 +23,11 @@ module aamux_controller( // UART TX&RX output uart_signal_tx, - input uart_signal_rx + input uart_signal_rx, + + // Seven-segment display + output [6:0] segments, + output [3:0] segments_anodes ); /// Clocks @@ -35,30 +40,49 @@ module aamux_controller( /// UART reg uart_latch; + wire uart_received; + reg uart_received_clear; + wire [7:0] uart_rx; wire uart_transmitted; uart_controller uart( .tx_data_in (data), .tx_data_latch (uart_latch), - .tx_clock (uart_clock), + .clock (uart_clock), .reset (reset), .tx_transmitted (uart_transmitted), - .tx_signal (uart_signal)); + .tx_signal (uart_signal_tx), + .rx_present (uart_received), + .rx_present_clear (uart_received_clear), + .rx_data (uart_rx), + .rx_signal (uart_signal_rx)); + + /// Seven-segment display + reg [15:0] to_display; + sevenseg display ( + .value (to_display), + .segments (segments), + .anodes (segments_anodes), + .sys_clock (sys_clock), + .reset (reset)); /// State machine reg [2:0] state; - `define ASSERT_ROW 0 - `define ROW_LATCH 1 - `define ASSERT_COL 2 - `define COL_LATCH 3 - `define WAITING 4 - `define OUTPUT 5 - `define OUTPUT_WAIT 6 - + `define WAIT_CMD 0 + `define ASSERT_ROW 1 + `define ROW_LATCH 2 + `define ASSERT_COL 3 + `define COL_LATCH 4 + `define WAITING 5 + `define OUTPUT 6 + `define OUTPUT_WAIT 7 + //assign leds = (1 << state); + assign leds = uart_received; + /// Address from which we will be reading, and + // how many bytes are left reg [21:0] read_address; - assign leds = read_address[21:14]; - + reg [16:0] bytes_left; /// sys_clock division into clock and uart_clock always @(posedge sys_clock) begin @@ -74,12 +98,25 @@ module aamux_controller( /// Main state machine code always @(posedge clock) begin if (reset) begin - state <= `ASSERT_ROW; + // Reset state + state <= `WAIT_CMD; read_address <= 0; + bytes_left <= 0; rowcol <= 1; uart_latch <= 0; + to_display <= 16'hDEAD; + uart_received_clear <= 0; end else begin case (state) + `WAIT_CMD: begin + if (uart_received) begin + state <= `ASSERT_ROW; + read_address <= uart_rx * 65536; + bytes_left <= 'h10000; + uart_received_clear <= 1; + end else + to_display <= 16'hDEAD; + end `ASSERT_ROW: begin address <= read_address[10:0]; state <= `ROW_LATCH; @@ -112,8 +149,14 @@ module aamux_controller( `OUTPUT_WAIT: begin if (!uart_transmitted) begin uart_latch <= 0; - state <= `ASSERT_ROW; + to_display <= bytes_left; read_address <= read_address + 1; + bytes_left <= bytes_left - 1; + if (bytes_left - 1 == 0) begin + uart_received_clear <= 0; + state <= `WAIT_CMD; + end else + state <= `ASSERT_ROW; end end endcase diff --git a/dump.py b/dump.py new file mode 100644 index 0000000..5790130 --- /dev/null +++ b/dump.py @@ -0,0 +1,23 @@ +import serial +import sys + +if len(sys.argv) < 2: + sys.stderr.write("Usage: {} /dev/ttySERIAL\n".format(sys.argv[0])) + sys.exit(1) + +s = serial.Serial(sys.argv[1], 115200) + +def dump_block(block): + s.write(chr(block)) + d = "" + while True: + d += s.read(1024) + print "[i] Receiving block {}, {} bytes received...".format(block, len(d)) + if len(d) == 65536: + return d + +for i in range(64): + data = dump_block(i) + f = open("dumps/dump-block-%02i.bin" % i, "w") + f.write(data) + f.close() diff --git a/dumps/dump-block-00.bin b/dumps/dump-block-00.bin new file mode 100644 index 0000000..b9cc53f Binary files /dev/null and b/dumps/dump-block-00.bin differ diff --git a/dumps/dump-block-01.bin b/dumps/dump-block-01.bin new file mode 100644 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current_anode; + wire [3:0] current_digit[0:3]; + assign current_digit[0] = value[3:0]; + assign current_digit[1] = value[7:4]; + assign current_digit[2] = value[11:8]; + assign current_digit[3] = value[15:12]; + + reg [10:0] clock_counter; + reg clock; + + always @(posedge sys_clock) + begin + if (clock_counter >= 1024) + begin + clock_counter <= 0; + clock <= !clock; + end else begin + clock_counter <= clock_counter + 1; + end + end + + always @(posedge clock) + begin + if (reset) begin + segments <= 0; + anodes <= 0; + current_anode <= 0; + end else begin + current_anode <= current_anode + 1; + anodes <= ~(1 << (3-current_anode)); + case (current_digit[current_anode]) + 4'h0: segments <= 7'b1000000; + 4'h1: segments <= 7'b1111001; + 4'h2: segments <= 7'b0100100; + 4'h3: segments <= 7'b0110000; + 4'h4: segments <= 7'b0011001; + 4'h5: segments <= 7'b0010010; + 4'h6: segments <= 7'b0000010; + 4'h7: segments <= 7'b1111000; + 4'h8: segments <= 7'b0000000; + 4'h9: segments <= 7'b0011000; + 4'hA: segments <= 7'b0001000; + 4'hB: segments <= 7'b0000011; + 4'hC: segments <= 7'b1000110; + 4'hD: segments <= 7'b0100001; + 4'hE: segments <= 7'b0000110; + 4'hF: segments <= 7'b0001110; + default: segments <= 7'b0110110; + endcase + end + end + +endmodule diff --git a/uart.v b/uart.v index 4e7432a..52cbe45 100644 --- a/uart.v +++ b/uart.v @@ -12,7 +12,7 @@ module uart_controller( input tx_data_latch, // baud rate clock - input tx_clock, + input clock, // reset line input reset, @@ -20,13 +20,20 @@ module uart_controller( // goes 1 when the UART finished transmitting output reg tx_transmitted, // the actual UART transmitter output - output reg tx_signal + output reg tx_signal, + + output reg rx_present, + input rx_present_clear, + output reg [7:0] rx_data, + + input rx_signal ); // Internal TX data (latched from tx_data_in) reg [7:0] tx_data; - reg [3:0] state; + reg [3:0] tx_state; + reg [3:0] rx_state; `define IDLE 0 `define START 1 `define BIT0 2 @@ -38,63 +45,122 @@ module uart_controller( `define BIT6 8 `define BIT7 9 `define STOP 10 - - always @(posedge tx_clock) + + /// Receiver + always @(posedge clock) begin if (reset) begin - state <= `IDLE; + rx_state <= `IDLE; + rx_present <= 0; + rx_data <= 0; + end else begin + if (rx_present_clear) + rx_present <= 0; + case (rx_state) + `IDLE: begin + if (!rx_signal) begin + // We received a start bit + rx_state <= `BIT0; + rx_present <= 0; + end + end + `BIT0: begin + rx_data[0] <= rx_signal; + rx_state <= `BIT1; + end + `BIT1: begin + rx_data[1] <= rx_signal; + rx_state <= `BIT2; + end + `BIT2: begin + rx_data[2] <= rx_signal; + rx_state <= `BIT3; + end + `BIT3: begin + rx_data[3] <= rx_signal; + rx_state <= `BIT4; + end + `BIT4: begin + rx_data[4] <= rx_signal; + rx_state <= `BIT5; + end + `BIT5: begin + rx_data[5] <= rx_signal; + rx_state <= `BIT6; + end + `BIT6: begin + rx_data[6] <= rx_signal; + rx_state <= `BIT7; + end + `BIT7: begin + rx_data[7] <= rx_signal; + rx_state <= `STOP; + end + `STOP: begin + rx_present <= 1; + rx_state <= `IDLE; + end + endcase + end + end + + /// Transmitter + always @(posedge clock) + begin + if (reset) begin + tx_state <= `IDLE; tx_signal <= 1; tx_data <= 0; tx_transmitted <= 1; end else begin - case (state) + case (tx_state) `IDLE: begin if (tx_data_latch) begin tx_data <= tx_data_in; - state <= `START; + tx_state <= `START; tx_transmitted <= 0; end end `START: begin tx_signal <= 0; - state <= `BIT0; + tx_state <= `BIT0; end `BIT0: begin tx_signal <= tx_data[0]; - state <= `BIT1; + tx_state <= `BIT1; end `BIT1: begin tx_signal <= tx_data[1]; - state <= `BIT2; + tx_state <= `BIT2; end `BIT2: begin tx_signal <= tx_data[2]; - state <= `BIT3; + tx_state <= `BIT3; end `BIT3: begin tx_signal <= tx_data[3]; - state <= `BIT4; + tx_state <= `BIT4; end `BIT4: begin tx_signal <= tx_data[4]; - state <= `BIT5; + tx_state <= `BIT5; end `BIT5: begin tx_signal <= tx_data[5]; - state <= `BIT6; + tx_state <= `BIT6; end `BIT6: begin tx_signal <= tx_data[6]; - state <= `BIT7; + tx_state <= `BIT7; end `BIT7: begin tx_signal <= tx_data[7]; - state <= `STOP; + tx_state <= `STOP; end `STOP: begin tx_signal <= 1; - state <= `IDLE; + tx_state <= `IDLE; tx_transmitted <= 1; end endcase