More work on APIC.
parent
05b3631004
commit
54a5e96722
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@ -115,7 +115,7 @@ hdd.img: kernel.bin
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emulate-nohdd-debug: kernel.bin
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@echo "[i] Starting GDB..."
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@echo -e "target remote localhost:1234\n" > gdbcommands
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@echo -e "file kernel.bin\ntarget remote localhost:1234\n" > gdbcommands
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@terminal -x /bin/bash -c "sleep 1 && gdb -x gdbcommands && rm gdbcommands" &
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@echo "[i] Starting QEmu..."
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@qemu-system-x86_64 --no-kvm -S -gdb tcp::1234 -d int -smp 4 -kernel ../Loader/loader.bin -initrd kernel.bin
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@ -16,6 +16,25 @@ x(7); \
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x(8); \
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x(9); \
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//Do something 10 times
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#define PPHAX_DO16(x) \
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x(0); \
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x(1); \
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x(2); \
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x(3); \
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x(4); \
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x(5); \
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x(6); \
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x(7); \
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x(8); \
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x(9); \
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x(10); \
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x(11); \
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x(12); \
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x(13); \
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x(14); \
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x(15); \
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//Do something 256 times
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#define PPHAX_DO256(x) \
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x(0); \
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@ -132,31 +132,31 @@ CPCIDevice::CPCIDevice(u16 Bus, u16 Device)
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u32 Value = ConfigRead(0, i);
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((u32 *)&m_Header)[i/4] = Value;
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}
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kprintf(" VID: %h, PID: %h\n", m_Header.VendorID, m_Header.ProductID);
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kprintf(" Type: ");
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switch (m_Header.HeaderType)
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{
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case 0x00:
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kprintf("Generic Device\n");
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break;
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case 0x01:
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kprintf("PCI-PCI Bridge\n");
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break;
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case 0x02:
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kprintf("CardBus Bridge\n");
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break;
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default:
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kprintf("Unknown.\n");
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break;
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}
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// kprintf(" VID: %h, PID: %h\n", m_Header.VendorID, m_Header.ProductID);
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// kprintf(" Type: ");
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// switch (m_Header.HeaderType)
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// {
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// case 0x00:
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// kprintf("Generic Device\n");
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// break;
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// case 0x01:
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// kprintf("PCI-PCI Bridge\n");
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// break;
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// case 0x02:
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// kprintf("CardBus Bridge\n");
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// break;
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// default:
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// kprintf("Unknown.\n");
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// break;
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// }
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kprintf(" Info: ");
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const s8 *VendorName, *ProductName, *ProductDescription;
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if (CPCIManager::DBGetVendor(m_Header.VendorID, &VendorName))
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kprintf("%s", VendorName);
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if (CPCIManager::DBGetProduct(m_Header.VendorID, m_Header.ProductID, &ProductName, &ProductDescription))
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kprintf(" %s %s", ProductName, ProductDescription);
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kprintf("\n");
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// kprintf(" Info: ");
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// const s8 *VendorName, *ProductName, *ProductDescription;
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// if (CPCIManager::DBGetVendor(m_Header.VendorID, &VendorName))
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// kprintf("%s", VendorName);
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// if (CPCIManager::DBGetProduct(m_Header.VendorID, m_Header.ProductID, &ProductName, &ProductDescription))
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// kprintf(" %s %s", ProductName, ProductDescription);
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// kprintf("\n");
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switch (m_Header.HeaderType)
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{
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@ -173,11 +173,11 @@ CPCIDevice::CPCIDevice(u16 Bus, u16 Device)
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if (Value == 0)
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continue;
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kprintf(" BAR%i: ", i);
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// kprintf(" BAR%i: ", i);
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if (Value & 1)
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{
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kprintf("I/O ");
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kprintf("Value: %x\n", Value);
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// kprintf("I/O ");
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// kprintf("Value: %x\n", Value);
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}
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else
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{
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@ -186,13 +186,13 @@ CPCIDevice::CPCIDevice(u16 Bus, u16 Device)
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kprintf(" non 32-bit, ignoring.\n");
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continue;
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}
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kprintf("Memory ");
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kprintf("Value: %x ", Value);
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// kprintf("Memory ");
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// kprintf("Value: %x ", Value);
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ConfigWrite(0, 0x10 + (i * 4), 0xFFFFFFFF);
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u32 NewValue = ConfigRead(0, 0x10 + (i * 4));
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// u32 NewValue = ConfigRead(0, 0x10 + (i * 4));
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ConfigWrite(0, 0x10 + (i * 4), Value);
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u32 Size = ~(NewValue & ~(0b1111)) + 1;
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kprintf("Size: %x (%ik)\n", Size, Size/1024);
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// u32 Size = ~(NewValue & ~(0b1111)) + 1;
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// kprintf("Size: %x (%ik)\n", Size, Size/1024);
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}
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}
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break;
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@ -2,11 +2,33 @@
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#include "Tier0/system.h"
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#include "Tier0/kstdio.h"
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#include "Tier0/paging.h"
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#include "Tier0/interrupts.h"
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#include "Tier0/panic.h"
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#define APIC_SET32(field, value) do { *((u32 *)(g_APIC.LAPIC + field)) = (value);} while(0)
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#define APIC_GET32(field) (*((u32*)(g_APIC.LAPIC + field)))
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#define APIC_SET32A(field, value) do { APIC_SET32(field, value); ASSERT(APIC_GET32(field) == (value));} while(0)
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struct {
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T_APIC_LAPIC *APIC;
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void *LAPIC;
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} g_APIC;
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void apic_eoi(void)
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{
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APIC_SET32(APIC_EOI, 0xFFFFFFFF);
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}
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void apic_spurious_interrupt(T_ISR_REGISTERS Registers)
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{
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}
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void apic_timer_interrupt(T_ISR_REGISTERS Registers)
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{
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kprintf("ohai\n");
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}
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void apic_enable_lapic(void)
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{
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u64 APICMSR = system_msr_get(0x1B);
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@ -16,13 +38,62 @@ void apic_enable_lapic(void)
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else
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{
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kprintf("[i] APIC enable flag not set in APIC MSR. Trying to set it...\n");
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APICMSR |= (1 << 22);
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APICMSR |= (1 << 11);
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system_msr_set(0x1B, APICMSR);
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}
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u64 Virtual = paging_minivmm_allocate();
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kprintf("[i] LAPIC will be @0x%x.\n", Virtual);
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paging_map_page(Virtual, 0xFEE00000);
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g_APIC.APIC = (T_APIC_LAPIC *)Virtual;
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g_APIC.LAPIC = (void *)Virtual;
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// reset APIC to a kinda known state
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APIC_SET32A(APIC_DFR, 0xFFFFFFFF);
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APIC_SET32(APIC_LDR, (APIC_GET32(APIC_LDR)&0x00FFFFFF)|1);
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APIC_SET32A(APIC_LVTTimer, 0x10000); // mask bit
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APIC_SET32A(APIC_LVTPerformanceCounter, 4 << 8); // NMI bit
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APIC_SET32A(APIC_LVTLINT0, 0x10000); // mask bit
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APIC_SET32A(APIC_LVTLINT1, 0x10000); // mask bit
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APIC_SET32A(APIC_TPR, 0); // task priority = 0 (accept all)
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// prepare interrupts ..
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interrupts_setup_isr(39, (void *)apic_spurious_interrupt, E_INTERRUPTS_RING0);
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interrupts_setup_isr(32, (void *)apic_timer_interrupt, E_INTERRUPTS_RING0);
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APIC_SET32A(APIC_SVR, 39 | 0x100); // spurious interrupt + sw enable bit
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APIC_SET32A(APIC_LVTTimer, 32); // apic timer interrupt
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APIC_SET32A(APIC_TimerDCR, 0x03); // timer divider = bus speed / 16
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kprintf("[i] LAPIC ready to calibrate timer.\n");
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// calibration time! let's use the PIT
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koutb(0x61, kinb(0x61) | 0xFD); // disable speaker
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koutb(0x43, 0xB2); // one shot, channel 2
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// to setup a 100Hz loop, wee need a divider of...
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// 1193180 / 100 Hz = 11931 = 0x2e9b
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koutb(0x42, 0x9b); // write low byte
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kinb(0x60); // wait a bit
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koutb(0x42, 0x2e); // write high bte
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// now we are ready to fire the PIT timer
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kprintf("[i] Firing PIT for calibration...\n");
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u8 Temporary = kinb(0x61) & 0xFE;
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koutb(0x61, Temporary); // gate low
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koutb(0x61, Temporary | 1); // gate high
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// don't forget to actually fire the APIC timer at the same time...
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APIC_SET32(APIC_TimerICR, 0xFFFFFFFF);
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// for(;;)
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// {
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// kprintf("APIC: %x\n", APIC_GET32(APIC_TimerICR));
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// }
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// wait for the PIT counter to reach zero...
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while (!(kinb(0x61) & 0x020));
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// disable APIC timer
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APIC_SET32(APIC_LVTTimer, 0x10000); // mask bit
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kprintf("[i] Timer reached zero, APIC Timer @%x.\n", APIC_GET32(APIC_TimerICR));
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}
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#undef APIC_SET
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@ -46,6 +46,9 @@ void exceptions_floating_point_isr(T_ISR_REGISTERS Registers)
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void exceptions_general_protection_isr(T_ISR_REGISTERS_ERR Registers)
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{
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T_ISR_REGISTERS NoErr;
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kprintf("general protection fault %x.\n", Registers.Error);
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__asm__ __volatile__("cli;");
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for (;;)
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RERR_TO_R(Registers, NoErr);
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PANIC_EX("General protection fault in kernel task.", NoErr);
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}
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@ -2,6 +2,7 @@
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#include "Tier0/paging.h"
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#include "Tier0/kstdio.h"
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#include "Tier0/pic.h"
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#include "preprocessor_hacks.h"
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struct {
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// IDT
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@ -113,10 +114,46 @@ void interrupts_setup_isr(u8 Interrupt, void *Handler, \
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*((u32*)&g_idt_entries[Interrupt]) = 0;
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}
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*/
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void interrupts_remap_pic(void)
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{
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// remap the PIC IRQ's to 0x20-0x27 and 0x28-0x2F
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// save masks
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u8 MaskMaster = kinb(0x21);
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u8 MaskSlave = kinb(0xA1);
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koutb(0x20, 0x11); // start initialization sequence
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koutb(0xA0, 0x11); // - " -
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koutb(0x21, 0x20); // master from 0x20
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koutb(0xA1, 0x28); // slave from 0x28
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koutb(0x21, 0x04); // slave PIC at IRQ2
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koutb(0xA1, 0x02); // cascade
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koutb(0x21, 0x01); // 8086 mode
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koutb(0xA1, 0x01); // 8086 mode
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// restore masks
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koutb(0x21, MaskMaster);
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koutb(0xA1, MaskSlave);
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}
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#define GENERIC_IRQ_DEF(i) void interrupts_irq##i##_isr(void) { kprintf("[w] OOPS: Unhandled IRQ"#i"\n"); }
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#define GENERIC_IRQ_BIND(i) interrupts_setup_isr(0x20 + i, (void *)interrupts_irq##i##_isr, E_INTERRUPTS_RING0)
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PPHAX_DO16(GENERIC_IRQ_DEF);
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void interrupts_init_simple(void)
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{
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interrupts_init_idt();
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interrupts_lidt();
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interrupts_remap_pic();
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// generic IRQ handlers
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PPHAX_DO16(GENERIC_IRQ_BIND);
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// enable hardware interrupts
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__asm__ __volatile__("sti;");
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kprintf("[i] Hardware interrupts enabled.\n");
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}
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/*
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void interrupts_irq_finish(u8 IRQ)
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